JPH0175816U

JPH0175816U -

Info

Publication number: JPH0175816U
Application number: JP1987171634U
Authority: JP
Priority date: 1987-11-10
Filing date: 1987-11-10
Publication date: 1989-05-23

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すレゾルバ・
デイジタル変換装置の構成を示す図、第２図は従
来のレゾルバ・デイジタル変換器を示す構成図、
第３図は第２図の主要部分の波形を示す図、第４
図は１８０度入力が入つてきた時の第２図の主要
部分の波形を示す図であり、図において、２は象
限選択器、３，３Ａ，３Ｂは余弦乗算器、４，４
Ａ，４Ｂは正弦乗算器、５は引き算器、７，７Ａ
，７Ｂは位相検波器、８は電圧制御発信器、９は
可逆カウンタ、１０は加算器、１１ａ，１１ｂは
電圧判定器、１２は論理ゲートである。なお、図
中同一符号は同一または相当部分を示すものとす
る。 Figure 1 shows a resolver showing an embodiment of this invention.
A diagram showing the configuration of a digital converter, FIG. 2 is a configuration diagram showing a conventional resolver digital converter,
Figure 3 shows the waveforms of the main parts of Figure 2;
The figure shows the waveforms of the main parts of Figure 2 when a 180 degree input is received. In the figure, 2 is a quadrant selector, 3, 3A, 3B are cosine multipliers, 4, 4
A, 4B is a sine multiplier, 5 is a subtracter, 7, 7A
, 7B is a phase detector, 8 is a voltage controlled oscillator, 9 is a reversible counter, 10 is an adder, 11a and 11b are voltage determiners, and 12 is a logic gate. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

Tracking type resolver digital conversion equipped with a sine multiplier, a cosine multiplier, an adder, a subtracter, a phase detector, a voltage judge, an AND gate, a voltage controlled oscillator, and a reversible counter. In the device, the sine wave signal of one of the two resolver signals is input to the first input terminal of the two input terminals, and the digital value of the reversible counter is input to the second input terminal, and the digital value is inputted to the second input terminal. A first cosine multiplier that multiplies cosines, a cosine wave signal of one of the two resolver signals is input to the first input terminal of the two input terminals, and the above-mentioned reversible counter is input to the second input terminal. a first sine multiplier that inputs a digital value and multiplies the digital value by the sine, and inputs the output signal of the first cosine multiplier to the first input terminal of the two input terminals, a subtracter that inputs the output signal of the first sine multiplier to a second input terminal and subtracts the two signals; and a subtracter that subtracts the two signals; a first phase detector which inputs the output signal of the detector, inputs the carrier wave to the second input terminal, detects and rectifies the carrier wave of the signal at the first input terminal, and the output signal of the first phase detector. a first voltage determiner that inputs the voltage value and determines the voltage value;
Input the sine wave signal of one of the two resolver signals to the first input terminal of the two input terminals, input the digital value of the reversible counter to the second input terminal, and multiply the digital value by the sine. a second sine multiplier, a cosine wave signal of one of the two resolver signals is input to the first input terminal of the two input terminals, and the digital value of the reversible counter is input to the second input terminal. A second cosine multiplier multiplies the input digital value by the cosine, and the output signal of the second sine multiplier is input to the first input terminal of the two input terminals, and the output signal of the second sine multiplier is input to the second input terminal. an adder that inputs the output signal of the second cosine multiplier and adds the two signals; and an adder that inputs the output signal of the adder to the first input terminal of the two input terminals, and A second phase detector that inputs a carrier wave and detects and rectifies the carrier wave of the signal at the first input terminal, and a second voltage determination that inputs the output signal of the second phase detector and determines the voltage value. The output signal of the first voltage determination circuit is inputted to the first input terminal of the circuit, and the output signal of the second voltage determination circuit is inputted to the second input terminal of the two input terminals. an AND gate that outputs a logic 1 when is 1; a voltage controlled oscillator that receives the output signal of the first phase detector and outputs a clock signal;
The output signal of the first phase detector is inputted to the first input terminal of the four input terminals, the clock signal of the voltage controlled oscillator is inputted to the second input terminal, and the clock signal of the voltage controlled oscillator is inputted to the third input terminal. 1. A resolver digital conversion device comprising: a reversible counter that receives an output signal of an AND gate, inputs a control signal to a fourth input terminal, and counts up or down.