JPH0158867B2 - - Google Patents

Info

Publication number
JPH0158867B2
JPH0158867B2 JP58200282A JP20028283A JPH0158867B2 JP H0158867 B2 JPH0158867 B2 JP H0158867B2 JP 58200282 A JP58200282 A JP 58200282A JP 20028283 A JP20028283 A JP 20028283A JP H0158867 B2 JPH0158867 B2 JP H0158867B2
Authority
JP
Japan
Prior art keywords
bumps
substrate
bump
film
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58200282A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6092648A (ja
Inventor
Kenzo Hatada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58200282A priority Critical patent/JPS6092648A/ja
Publication of JPS6092648A publication Critical patent/JPS6092648A/ja
Publication of JPH0158867B2 publication Critical patent/JPH0158867B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors

Landscapes

  • Wire Bonding (AREA)
JP58200282A 1983-10-26 1983-10-26 バンプ形成用基板およびこれを用いたバンプ形成方法 Granted JPS6092648A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58200282A JPS6092648A (ja) 1983-10-26 1983-10-26 バンプ形成用基板およびこれを用いたバンプ形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58200282A JPS6092648A (ja) 1983-10-26 1983-10-26 バンプ形成用基板およびこれを用いたバンプ形成方法

Publications (2)

Publication Number Publication Date
JPS6092648A JPS6092648A (ja) 1985-05-24
JPH0158867B2 true JPH0158867B2 (enExample) 1989-12-13

Family

ID=16421720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58200282A Granted JPS6092648A (ja) 1983-10-26 1983-10-26 バンプ形成用基板およびこれを用いたバンプ形成方法

Country Status (1)

Country Link
JP (1) JPS6092648A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63160352A (ja) * 1986-12-24 1988-07-04 Semiconductor Energy Lab Co Ltd 半導体装置の実装方法

Also Published As

Publication number Publication date
JPS6092648A (ja) 1985-05-24

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