JPH0145784B2 - - Google Patents

Info

Publication number
JPH0145784B2
JPH0145784B2 JP58007959A JP795983A JPH0145784B2 JP H0145784 B2 JPH0145784 B2 JP H0145784B2 JP 58007959 A JP58007959 A JP 58007959A JP 795983 A JP795983 A JP 795983A JP H0145784 B2 JPH0145784 B2 JP H0145784B2
Authority
JP
Japan
Prior art keywords
data
bit
sfr
transmission line
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58007959A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59133752A (ja
Inventor
Toshio Awaji
Kenichi Yukimatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP795983A priority Critical patent/JPS59133752A/ja
Publication of JPS59133752A publication Critical patent/JPS59133752A/ja
Publication of JPH0145784B2 publication Critical patent/JPH0145784B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
JP795983A 1983-01-20 1983-01-20 多重デ−タ送出方式 Granted JPS59133752A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP795983A JPS59133752A (ja) 1983-01-20 1983-01-20 多重デ−タ送出方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP795983A JPS59133752A (ja) 1983-01-20 1983-01-20 多重デ−タ送出方式

Publications (2)

Publication Number Publication Date
JPS59133752A JPS59133752A (ja) 1984-08-01
JPH0145784B2 true JPH0145784B2 (enrdf_load_html_response) 1989-10-04

Family

ID=11680020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP795983A Granted JPS59133752A (ja) 1983-01-20 1983-01-20 多重デ−タ送出方式

Country Status (1)

Country Link
JP (1) JPS59133752A (enrdf_load_html_response)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6361522A (ja) * 1986-09-01 1988-03-17 Fujitsu Ltd 時分割多重装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5045738U (enrdf_load_html_response) * 1973-08-22 1975-05-08
JPS50150985A (enrdf_load_html_response) * 1974-05-23 1975-12-04

Also Published As

Publication number Publication date
JPS59133752A (ja) 1984-08-01

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