JPH0142143B2 - - Google Patents

Info

Publication number
JPH0142143B2
JPH0142143B2 JP56071517A JP7151781A JPH0142143B2 JP H0142143 B2 JPH0142143 B2 JP H0142143B2 JP 56071517 A JP56071517 A JP 56071517A JP 7151781 A JP7151781 A JP 7151781A JP H0142143 B2 JPH0142143 B2 JP H0142143B2
Authority
JP
Japan
Prior art keywords
layer
polysilicon
insulating layer
forming
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56071517A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5715463A (en
Inventor
Aaru Gaadeinaa Jeemuzu
Aaru Makareuitsukuzu Sutanree
Reuitsutsu Maatein
Efu Shepaado Josefu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5715463A publication Critical patent/JPS5715463A/ja
Publication of JPH0142143B2 publication Critical patent/JPH0142143B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
JP7151781A 1980-06-30 1981-05-14 Method of forming contact for double polysilicon semiconductor device Granted JPS5715463A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/164,647 US4394406A (en) 1980-06-30 1980-06-30 Double polysilicon contact structure and process

Publications (2)

Publication Number Publication Date
JPS5715463A JPS5715463A (en) 1982-01-26
JPH0142143B2 true JPH0142143B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-09-11

Family

ID=22595441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7151781A Granted JPS5715463A (en) 1980-06-30 1981-05-14 Method of forming contact for double polysilicon semiconductor device

Country Status (4)

Country Link
US (1) US4394406A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0042947B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5715463A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3165364D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020564A (ja) * 1983-07-13 1985-02-01 Matsushita Electronics Corp 半導体装置の製造方法
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4505026A (en) * 1983-07-14 1985-03-19 Intel Corporation CMOS Process for fabricating integrated circuits, particularly dynamic memory cells
US4744858A (en) * 1985-03-11 1988-05-17 Texas Instruments Incorporated Integrated circuit metallization with reduced electromigration
JPS61222248A (ja) * 1985-03-28 1986-10-02 Toshiba Corp 半導体装置及びその製造方法
JPH0719541B2 (ja) * 1985-04-30 1995-03-06 株式会社日立製作所 インライン型カラー受像管
JPH03156927A (ja) * 1989-10-24 1991-07-04 Hewlett Packard Co <Hp> アルミ・メタライゼーションのパターン形成方法
JP2684996B2 (ja) * 1994-08-19 1997-12-03 株式会社日立製作所 インライン形カラー陰極線管
US5506172A (en) * 1994-08-29 1996-04-09 Micron Technology, Inc. Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer
US6740573B2 (en) * 1995-02-17 2004-05-25 Micron Technology, Inc. Method for forming an integrated circuit interconnect using a dual poly process
TW414913B (en) 1997-10-20 2000-12-11 Toshiba Corp The cathode ray tube
TW440885B (en) 1998-03-13 2001-06-16 Toshiba Corp Cathode-ray tube
US6429101B1 (en) * 1999-01-29 2002-08-06 International Business Machines Corporation Method of forming thermally stable polycrystal to single crystal electrical contact structure
US6583460B1 (en) 2000-08-29 2003-06-24 Micron Technology, Inc. Method of forming a metal to polysilicon contact in oxygen environment
JP2007165401A (ja) * 2005-12-09 2007-06-28 Nec Electronics Corp 半導体装置および半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3479237A (en) * 1966-04-08 1969-11-18 Bell Telephone Labor Inc Etch masks on semiconductor surfaces
US4251571A (en) * 1978-05-02 1981-02-17 International Business Machines Corporation Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon

Also Published As

Publication number Publication date
DE3165364D1 (en) 1984-09-13
EP0042947A1 (en) 1982-01-06
EP0042947B1 (en) 1984-08-08
JPS5715463A (en) 1982-01-26
US4394406A (en) 1983-07-19

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