JPH0141265B2 - - Google Patents

Info

Publication number
JPH0141265B2
JPH0141265B2 JP59267946A JP26794684A JPH0141265B2 JP H0141265 B2 JPH0141265 B2 JP H0141265B2 JP 59267946 A JP59267946 A JP 59267946A JP 26794684 A JP26794684 A JP 26794684A JP H0141265 B2 JPH0141265 B2 JP H0141265B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
die pad
resin
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59267946A
Other languages
English (en)
Other versions
JPS61144046A (ja
Inventor
Tsuneo Hashizume
Hirotsugu Harada
Hirobumi Ikeo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59267946A priority Critical patent/JPS61144046A/ja
Publication of JPS61144046A publication Critical patent/JPS61144046A/ja
Publication of JPH0141265B2 publication Critical patent/JPH0141265B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ダイパツドに半導体チツプを固着
し、樹脂封止した半導体装置に関する。
〔従来の技術〕
従来のこの種の半導体装置は、第２図に断面図
で示すようになつていた。１はシリコン材などか
らなる半導体チツプで、リードフレームのダイパ
ツド２上にろう材３により接合固着されている。
ろう材３には金―シリコン、銀ペースト又ははん
だなどを用いている。こうして、半導体チツプ１
の発熱がダイパツド２に伝達放散されるようにし
ている。半導体チツプ１上の電極パツド４と外部
リード５とを、金属細線６でワイヤボンデイング
している。７は注型成形により半導体チツプ１部
を封止した樹脂封止体である。
上記従来の装置において、注型された封止樹脂
が硬化時に収縮する。半導体チツプ１はダイパツ
ド２上に全面で接着されているが、上記樹脂の収
縮に対し、半導体チツプ１が小さく、チツプ面の
配線パターンも3μm以上あつて比較的集積度が高
くない場合は、問題とはならなかつた。
〔発明が解決しようとする問題点〕
上記のような従来の半導体装置では、半導体チ
ツプ１の長辺が５mmを超え、配線パターンが3μm
より小さくなつた場合は、半導体チツプ１に形成
されてある個別要素も小さくなる。この場合、封
止樹脂の硬化時の収縮により、半導体チツプ１は
水平方向の圧縮力を受ける。しかし、下面は剛性
の大きいダイパツド２に全面接着されていて収縮
が阻止される。半導体チツプ１表面に接している
封止樹脂が中心に向つて収縮するが、このとき、
半導体チツプ１の辺が短いと問題にはならない
が、辺が長いと中心から距離が遠い周辺側では封
止樹脂が収縮により動く度合いが大きくなる。こ
の収縮移動をする封止樹脂に接した、半導体チツ
プ１周辺部でのアルミなどの配線などが、変形な
どの損傷を受ける問題点があつた。また、さら
に、半導体チツプ１にパツシベーシヨン（図示は
略す）を施してある場合は、このパツシーベーシ
ヨンにクラツクを生じ、防湿が阻害され湿気の浸
入により電気特性不良となるなどの問題点があつ
た。
この発明は、このような問題点を解決するため
になされたもので、封止樹脂の硬化時の収縮によ
る半導体チツプの表面部の要素の損傷をなくし、
品質を向上した半導体装置を得ることを目的とし
ている。特に、半導体チツプが長方形をなし、短
辺が３mm以下で長辺が３mmを超える場合に好適で
ある。
〔問題点を解決するための手段〕
この発明にかかる半導体装置は、ダイパツドを
複数の山部をもつ波形に形成し、半導体チツプを
長手方向を波形の方向にして各山部上にろう付け
固着したものである。
〔作 用〕
封止樹脂が硬化により収縮すると、半導体チツ
プに圧縮力が加わるが、最も影響のの大きい長辺
方向に対しては、ダイパツドが波形をなしていて
たわむことができるので、半導体チツプは抑制さ
れずに封止樹脂の収縮に順応して縮むことがき
る。
〔実施例〕
第１図はこの発明による半導体装置の一実施例
の要部の拡大断面図である。１１はダイパツド
で、複数の山部１１ａをもつ角形の波形に形成さ
れている。半導体チツプ１は短辺が３mm以下で、
長辺が３mmを超えた長方形であり、長手方向を波
形の方向にし、各山部１１ａ上にろう付け固着し
ている。半導体チツプ１の各電極パツド４と外部
リード５とを金属細線６でワイヤボンデイングし
ている。この半導体チツプ１部を樹脂の注型成形
による樹脂封止体７で封止している。
上記一実施例の装置において、封止樹脂が硬化
により収縮すると、半導体チツプ１が圧縮力を受
けて中心に向つて収縮しようとする。半導体チツ
プ１を接着しているダイパツド１１は、波形にな
つていて、たわみ性が大きく、半導体チツプ１の
収縮を阻害することなく、順応させる。これによ
り封止樹脂が中心部に向つて収縮しても、半導体
チツプ１も順応して収縮され、表面部の周辺部の
要素が損傷を受けることがない。また、半導体チ
ツプ１部にパツシベーシヨンが施されてある場合
は、パツシベーシヨンのクラツク発生が防止され
る。
なお、上記実施例ではダイバツド１１の波形は
角形にしたが、円弧状にしてもよい。
〔発明の効果〕
以上のように、この発明によれば、ダイパツド
を複数の山部をもつ波形に形成し、半導体チツプ
を長手方向を波形の方向にして各山部上にろう付
け固着したので、封止樹脂の硬化時の収縮による
半導体チツプの表面部の要素の損傷が防止され、
品質を向上することができる。
【図面の簡単な説明】
第１図はこの発明による半導体装置の一実施例
の要部の拡大断面図、第２図は従来の半導体装置
の断面図である。 １……半導体チツプ、２……ダイパツド、３…
…ろう材、４……電極パツド、５……外部リー
ド、６……金属細線、７……樹脂封止体、１１…
…ダイパツド、１１ａ……山部。なお、図中同一
符号は同一又は相当部分を示す。

Claims (1)

    【特許請求の範囲】
  1. １ ダイパツド上に半導体チツプを固着し、樹脂
    封止体で囲い封止した半導体装置において、上記
    ダイパツドを複数の山部をもつ波形に形成し、上
    記半導体チツプを長手方向を上記波形の方向にし
    て各山部上にろう付け固着したことを特徴とする
    半導体装置。
JP59267946A 1984-12-17 1984-12-17 半導体装置 Granted JPS61144046A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59267946A JPS61144046A (ja) 1984-12-17 1984-12-17 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59267946A JPS61144046A (ja) 1984-12-17 1984-12-17 半導体装置

Publications (2)

Publication Number Publication Date
JPS61144046A JPS61144046A (ja) 1986-07-01
JPH0141265B2 true JPH0141265B2 (ja) 1989-09-04

Family

ID=17451797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59267946A Granted JPS61144046A (ja) 1984-12-17 1984-12-17 半導体装置

Country Status (1)

Country Link
JP (1) JPS61144046A (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125458U (ja) * 1991-05-07 1992-11-16 山口日本電気株式会社 リードフレーム
JP3389357B2 (ja) * 1994-11-29 2003-03-24 新光電気工業株式会社 半導体チップ搭載用基板
KR100386061B1 (ko) * 1995-10-24 2003-08-21 오끼 덴끼 고오교 가부시끼가이샤 크랙을방지하기위한개량된구조를가지는반도체장치및리이드프레임
JP4925401B2 (ja) * 2005-07-04 2012-04-25 日本クラウンコルク株式会社 流通時の開封防止機能を備えた注出具

Also Published As

Publication number Publication date
JPS61144046A (ja) 1986-07-01

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