JPH0126093B2 - - Google Patents

Info

Publication number
JPH0126093B2
JPH0126093B2 JP16905682A JP16905682A JPH0126093B2 JP H0126093 B2 JPH0126093 B2 JP H0126093B2 JP 16905682 A JP16905682 A JP 16905682A JP 16905682 A JP16905682 A JP 16905682A JP H0126093 B2 JPH0126093 B2 JP H0126093B2
Authority
JP
Japan
Prior art keywords
input
resources
program
queue
slowdown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16905682A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5958552A (ja
Inventor
Takanao Hiraoka
Minoru Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16905682A priority Critical patent/JPS5958552A/ja
Publication of JPS5958552A publication Critical patent/JPS5958552A/ja
Publication of JPH0126093B2 publication Critical patent/JPH0126093B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP16905682A 1982-09-28 1982-09-28 スロ−ダウン制御方式 Granted JPS5958552A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16905682A JPS5958552A (ja) 1982-09-28 1982-09-28 スロ−ダウン制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16905682A JPS5958552A (ja) 1982-09-28 1982-09-28 スロ−ダウン制御方式

Publications (2)

Publication Number Publication Date
JPS5958552A JPS5958552A (ja) 1984-04-04
JPH0126093B2 true JPH0126093B2 (OSRAM) 1989-05-22

Family

ID=15879516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16905682A Granted JPS5958552A (ja) 1982-09-28 1982-09-28 スロ−ダウン制御方式

Country Status (1)

Country Link
JP (1) JPS5958552A (OSRAM)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123234A (ja) * 1990-09-14 1992-04-23 Hitachi Ltd マルチプロセッサのプロセススケジューリング方式及びメモリ管理方式
US7865684B2 (en) * 2005-06-27 2011-01-04 Ab Initio Technology Llc Managing message queues

Also Published As

Publication number Publication date
JPS5958552A (ja) 1984-04-04

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