JPH0124373B2 - - Google Patents

Info

Publication number
JPH0124373B2
JPH0124373B2 JP56113224A JP11322481A JPH0124373B2 JP H0124373 B2 JPH0124373 B2 JP H0124373B2 JP 56113224 A JP56113224 A JP 56113224A JP 11322481 A JP11322481 A JP 11322481A JP H0124373 B2 JPH0124373 B2 JP H0124373B2
Authority
JP
Japan
Prior art keywords
delay
delay circuit
circuit
period
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56113224A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5814622A (ja
Inventor
Kenji Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP56113224A priority Critical patent/JPS5814622A/ja
Priority to US06/400,036 priority patent/US4504749A/en
Publication of JPS5814622A publication Critical patent/JPS5814622A/ja
Publication of JPH0124373B2 publication Critical patent/JPH0124373B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/0026—Layout of the delay element using circuits having two logic levels using memories or FIFO's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00267—Layout of the delay element using circuits having two logic levels using D/A or A/D converters

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP56113224A 1981-07-20 1981-07-20 遅延回路 Granted JPS5814622A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56113224A JPS5814622A (ja) 1981-07-20 1981-07-20 遅延回路
US06/400,036 US4504749A (en) 1981-07-20 1982-07-20 Delay pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56113224A JPS5814622A (ja) 1981-07-20 1981-07-20 遅延回路

Publications (2)

Publication Number Publication Date
JPS5814622A JPS5814622A (ja) 1983-01-27
JPH0124373B2 true JPH0124373B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-05-11

Family

ID=14606708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56113224A Granted JPS5814622A (ja) 1981-07-20 1981-07-20 遅延回路

Country Status (2)

Country Link
US (1) US4504749A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5814622A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536855A (en) * 1982-12-23 1985-08-20 International Telephone And Telegraph Corporation Impedance restoration for fast carry propagation
JPS6068713A (ja) * 1983-09-26 1985-04-19 Nec Corp タイミング調整回路
US4593207A (en) * 1984-04-05 1986-06-03 The United States Of America As Represented By The Secretary Of The Army Synchronizer circuit for synchronizing the scan of a device with an externally received triggering signal
JPS60229521A (ja) * 1984-04-27 1985-11-14 Sony Tektronix Corp デジタル信号遅延回路
JPS6139619A (ja) * 1984-07-30 1986-02-25 Nec Corp クロツクパルス分配回路
US5027315A (en) * 1984-09-28 1991-06-25 Advanced Micro Devices, Inc. Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions
US4737670A (en) * 1984-11-09 1988-04-12 Lsi Logic Corporation Delay control circuit
US4686458A (en) * 1985-05-31 1987-08-11 Hughes Aircraft Company Pulse alignment system
US4658161A (en) * 1985-08-13 1987-04-14 Hewlett-Packard Company Split phase loop
US4660197A (en) * 1985-11-01 1987-04-21 Teradyne, Inc. Circuitry for synchronizing a multiple channel circuit tester
JPS62171315A (ja) * 1986-01-16 1987-07-28 タンデム　コンピユ−タ−ズ　インコ−ポレ−テツド 遅延調整回路
JPH0681018B2 (ja) * 1986-03-31 1994-10-12 三菱電機株式会社 半導体集積回路
US4812769A (en) * 1986-04-30 1989-03-14 Tektronix, Inc. Programmable sampling time base circuit
US4745310A (en) * 1986-08-04 1988-05-17 Motorola, Inc. Programmable delay circuit
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
JPH0627108Y2 (ja) * 1986-11-05 1994-07-27 マミヤ・オーピー株式会社 両軸受リ−ル
US4748348A (en) * 1986-12-29 1988-05-31 Tektronix, Inc. Multi-level pattern detector for a single signal
JPH01144719A (ja) * 1987-11-30 1989-06-07 Toshiba Corp リトリガブル・マルチバイブレータ
US5087842A (en) * 1988-01-06 1992-02-11 Digital Equipment Corporation Delay circuit having one of a plurality of delay lines which may be selected to provide an operation of a ring oscillator
US4868430A (en) * 1988-02-11 1989-09-19 Ncr Corporation Self-correcting digitally controlled timing circuit
JPH02130126U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1988-08-06 1990-10-26
US5013944A (en) * 1989-04-20 1991-05-07 International Business Machines Corporation Programmable delay line utilizing measured actual delays to provide a highly accurate delay
JPH02296410A (ja) * 1989-05-11 1990-12-07 Mitsubishi Electric Corp 遅延回路
US5140202A (en) * 1989-06-05 1992-08-18 Hewlett-Packard Company Delay circuit which maintains its delay in a given relationship to a reference time interval
US5258660A (en) * 1990-01-16 1993-11-02 Cray Research, Inc. Skew-compensated clock distribution system
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
US5192886A (en) * 1990-03-15 1993-03-09 Hewlett-Packard Company Sub-nanosecond calibrated delay line structure
US5175453A (en) * 1990-08-15 1992-12-29 Lsi Logic Corporation Configurable pulse generator, especially for implementing signal delays in semiconductor devices
US5237224A (en) * 1990-10-11 1993-08-17 International Business Machines Corporation Variable self-correcting digital delay circuit
JPH04157379A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 遅延測定方式
US5175452A (en) * 1991-09-30 1992-12-29 Data Delay Devices, Inc. Programmable compensated digital delay circuit
US5214680A (en) * 1991-11-01 1993-05-25 Hewlett-Packard Company CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration
US5283631A (en) * 1991-11-01 1994-02-01 Hewlett-Packard Co. Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
US5233637A (en) * 1991-11-01 1993-08-03 Hewlett-Packard Company System for generating an analog regulating voltage
US5243227A (en) * 1991-11-01 1993-09-07 Hewlett-Packard Company Fine/coarse wired-or tapped delay line
JP3605122B2 (ja) * 1991-12-13 2004-12-22 テキサス インスツルメンツ インコーポレイテツド 補償回路と遅延を補償する方法
US5180937A (en) * 1992-02-28 1993-01-19 Lsi Logic Corporation Delay compensator and monitor circuit having timing generator and sequencer
JPH0613857A (ja) * 1992-06-25 1994-01-21 Fujitsu Ltd ディレイ調整回路
US5289060A (en) * 1992-09-16 1994-02-22 Texas Instruments Incorporated Programmable glitch filter
US5394024A (en) * 1992-12-17 1995-02-28 Vlsi Technology, Inc. Circuit for eliminating off-chip to on-chip clock skew
US5900761A (en) * 1995-01-24 1999-05-04 Advantest Corporation Timing generating circuit and method
US5789969A (en) * 1996-03-15 1998-08-04 Adaptec, Inc. Digital delay circuit and method
EP0817200B1 (en) * 1996-06-28 2003-03-19 STMicroelectronics S.r.l. Clock circuit for reading a multilevel non volatile memory cells device
US5859553A (en) * 1997-01-08 1999-01-12 Microchip Technology Incorporated System and method for a glitchless transition between differing delay paths
US6275085B1 (en) * 1999-05-24 2001-08-14 Micron Technology, Inc. Comparator for determining process variations
US6441666B1 (en) 2000-07-20 2002-08-27 Silicon Graphics, Inc. System and method for generating clock signals
US7185239B2 (en) * 2003-09-29 2007-02-27 Stmicroelectronics Pvt. Ltd. On-chip timing characterizer
DE102004021163A1 (de) * 2004-04-29 2005-08-11 Infineon Technologies Ag Verfahren und Messsystem zum Messen einer Verzögerungszeit eines Verzögerungselementes in einer integrierten Schaltung
US7254505B2 (en) * 2005-06-29 2007-08-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for calibrating delay lines
JP2007235908A (ja) * 2006-02-02 2007-09-13 Sharp Corp リング発振回路、遅延時間測定回路、テスト回路、クロック発生回路、イメージセンサ、パルス発生回路、半導体集積回路、及び、そのテスト方法
JP5292243B2 (ja) * 2009-09-28 2013-09-18 株式会社日立製作所 半導体集積回路
US11835580B2 (en) * 2020-12-01 2023-12-05 Mediatek Singapore Pte. Ltd. Circuit and method to measure simulation to silicon timing correlation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2931981A (en) * 1957-09-20 1960-04-05 Mackay Radio & Telegraph Co Variable pulse delay apparatus
US3150324A (en) * 1961-02-03 1964-09-22 Cutler Hammer Inc Interleaved delay line with recirculating loops for permitting continuous storage and desired delay time
US3712994A (en) * 1971-07-20 1973-01-23 Int Standard Electric Corp Automatic time control circuit

Also Published As

Publication number Publication date
JPS5814622A (ja) 1983-01-27
US4504749A (en) 1985-03-12

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