JPH01243033A - Thin film transistor - Google Patents

Abstract

PURPOSE:To eliminate variance in parasitic capacity and to reduce the parasitic capacity by providing a drain electrode which is arranged in parallel to two source electrodes to specific length while the line width is specified and a gate electrode which is formed on a semiconductor layer across a gate insulating film. CONSTITUTION:This thin film transistor is equipped with the two source electrodes 103 which are arranged at a specific interval in parallel to specific line width and length, the drain electrode 102 which is wired between those source electrodes 103 in parallel to the source electrodes to the specific length so that Y1<(6+1.2XW)(3+0.6X)/(6+W/2)(mum) holds for the line width Y1mum, the semiconductor layer 104 provided crossing the lengthwise direction of the two source electrodes 103 and drain electrode 102, and the gate electrode provided on the semiconductor layer 104 across the gate insulation film 105. Consequently, there is no variance in the parasitic capacity, which is reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor applied to active matrix liquid crystal displays, image sensors, three-dimensional integrated circuits, and the like.

[Conventional technology]

Conventional thin film transistors are, for example, JAPAN DIS
It had a structure as shown in PLAY '86, 1986, pages 196 to 199. This structure is generalized and its outline is shown in FIG. (a) The figure is a top view, and (b)
The figure is a cross-sectional view at AA'. A source region 202 and a drain region 203 are formed on an insulating substrate 201 made of glass, quartz, sapphire, etc., which are made of a polycrystalline silicon thin film doped with impurities to serve as donors or acceptors. A source electrode 204 and a drain electrode 205 are provided in contact with this, and a channel region 206 made of a polycrystalline silicon thin film is formed so as to contact and connect above the source region 202 and drain region 203. A gate insulating film 207 covers these.
is provided. Furthermore, a gate electrode 208 is provided in contact with this.

[Problem to be solved by the invention]

However, conventional thin film transistors have the following problems.

FIG. 3 shows a top view of the thin film transistor, and FIG. 4 shows its equivalent circuit.

A parasitic capacitance 401 is formed between the gate electrode 304 and the gate G and source S using the gate insulating film as a dielectric in the shaded area S1 shown in FIG. 3(a). Similarly, gate electrode 30
4 and the parasitic capacitance j between the gate G and the drain D at the shaded area S2
t402 is formed.

As shown in FIG. 3(b), when a pattern shift of the gate electrode 304 occurs in the direction of the arrow 305, the parasitic capacitance 401 decreases and the parasitic capacitance j1402 increases.

Conversely, if the pattern of the gate electrode #71304 is misaligned in the direction of the arrow 306 as shown in FIG. 3(c), the parasitic capacitance 4
01 increases, and the parasitic capacitance Jit402 decreases. In other words, the parasitic capacitance of the thin film transistor is the gate voltage '[! 3
The main causes of the pattern deviation, which varies greatly due to the pattern deviation of 04, are the alignment deviation of the gate 7X'1!1304, the pitch deviation between photomasks, etc. Therefore, parasitic capacitance varies within the same substrate or between substrates, making it difficult to maintain constant circuit constants, resulting in variations in display quality when applied to liquid crystal displays, and deteriorating image quality. Furthermore, as the size of the liquid crystal display increases, the pattern deviation becomes even larger, significantly degrading the display quality and becoming a major hindrance to increasing the size of the display.

When applied to image sensors and three-dimensional integrated circuits, it is difficult to maintain constant circuit constants, which has been a major hindrance to practical application.

The present invention solves these problems.

The purpose is to provide a thin film transistor with small parasitic capacitance and no variation in parasitic capacitance.

[Means to solve the problem]

FJ thin film transistor of the present invention (a) Two source electrodes are wired parallel to the specified length with a predetermined line width at a predetermined interval, and the two source electrodes are connected between the two source electrodes. Line width Y, (μm) parallel to the source electrode
Gas.

Y+<(6+1.2.5W)(3+0.6X)/'(6
+W/2) fμml.

X is the length of the substrate in the longitudinal direction (am), W is the channel width of the thin film transistor (μm),
A drain electrode wired to a predetermined length, a semiconductor layer provided in a direction intersecting the longitudinal direction of the two source electrodes and the train electrode, and a semiconductor layer provided on the semiconductor layer with a gate insulating film interposed therebetween. Install the gate electrode.

(b) The line width Y2 (μm) of the two source electrodes is Yx
<2 (3+0.6X) 27' (12+W)
It is characterized by satisfying (μ'').

〔Example〕

The present invention will be described in detail below based on Examples. 1st
An example of a thin film transistor according to the present invention is shown in the figure (a
) is a top view, and (b) is a sectional view at BB'. On an insulating substrate 101 made of glass, quartz, sapphire, etc., two source electrodes 103 made of silicon thin films such as polycrystalline silicon, amorphous silicon, etc. doped with impurities to serve as donors or acceptors are provided in parallel to each other. ing. Two source electrodes 8 made of the same material as the source electrodes.
i! 103, the drain electrode 102 is connected to the source electrode 1
It is provided so as to be parallel to 03.

Also, the line width of the source electrode 103 and the drain electrode 102 is 2.
The upper side of this source electrode 103 and the drain electrode 10 are preferably 0 μm or less and have a thickness of 500 to 5000.
A semiconductor layer 104 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is formed in contact with the upper side of the semiconductor layer 2 in a direction crossing the longitudinal direction. The film thickness is 200O
A source wiring 108 made of a metal, a transparent conductive film, etc., which is preferably less than A, is in contact with the two source electrodes 103 , and a train wiring 107 is likewise in contact with the drain electrode 102 . A gate insulating film 105 of SiO□, 5iON, etc. covers all of these.

On this, a gate electrode 106 made of metal, transparent conductive film, etc.
covers the semiconductor layer 104 with a gate insulating film 105 interposed therebetween. The gate insulating film 105 also serves as an interlayer insulating film that maintains insulation between wirings. A thin film transistor configured in this manner is equivalent to two thin film transistors connected in parallel.

The channel length of a thin film transistor is indicated by arrow 10 in FIG.
9, and the distance between the two parallel source electrodes 103 is twice the channel length plus the line width of the drain electrode 102. Also, the channel width W is twice the value indicated by arrow 110.

FIG. 5 shows a main view of the thin film transistor of the present invention, and FIG. 6 shows its equivalent circuit.

The gate electrode 506 and the hatched areas S3 and S shown in FIG.
Parasitic capacitances 601 and 602 are formed between them. Similarly, gate electric fl! A parasitic capacitance 603 is formed between the gate G and the drain D at 506 and the shaded area S. As shown in FIG. 5(b), even if a pattern shift of the gate electrode 506 occurs in the direction of the arrow 511, the area of 33.34, Ss remains constant without changing at all, and as a result, the parasitic capacitance 601
．． 602 and 603 are not affected by pattern deviation at all and are constant. Furthermore, as shown in FIG. 5(C), the gate electrode 5
The same thing applies even if pattern shift occurs in the direction of arrow 512 in 06. When a pattern shift occurs in the direction shown in FIG. 5(d), the area of S is the same as when there is no pattern shift, but the area of Ss and S changes. In other words, the parasitic capacitance 601 becomes larger and the parasitic capacitance 602 becomes smaller, but as is clear from the equivalent circuit shown in FIG. Same as when there is no (36+S?
=Ss +Ss), and the case of Fig. 5(e) is exactly the same (ss +39 =83-1-SS).0 As explained above, no matter which direction the pattern shift occurs, the parasitic capacitance of the thin film transistor is , always remains constant. That is, it is possible to eliminate variations in parasitic capacitance within the same substrate or between substrates.

Glass substrates are widely used as insulating substrates for forming thin film transistors. Generally, when a glass substrate is heat-treated and returned to room temperature, the dimensions after the heat treatment become smaller than the dimensions of the glass before the heat treatment.

(Hereinafter referred to as substrate shrinkage) As an example, FIG. 7 shows the shrinkage of a #7059 (manufactured by Corning) substrate, where the horizontal axis shows the heat treatment temperature and the vertical axis shows the amount of substrate shrinkage per 10 cm.
As is clear from FIG. 6, heat treatment at 500° C. or higher causes rapid shrinkage of the substrate.

When the semiconductor layer 504 is made of a semiconductor formed at a high temperature of 500° C. or higher, such as polycrystalline silicon, the substrate shrinks after the semiconductor is formed, and the semiconductor layer 504 and the gate electrode [! The pattern deviation of 506 becomes large.

This will be explained using FIG. After forming a source electrode 801 and a drain electrode 802 and patterning them into the shape shown in FIG. 8, a semiconductor layer 803 is formed. semiconductor layer 8
Shrinkage of the substrate occurs during the formation of 03. Therefore, the semiconductor layer 8
03. The pattern deviation of the gate electrode 804, source wiring 805, and drain wiring 806 must take into account the shrinkage of the substrate.Here, the pattern deviation due to alignment accuracy, photomask pitch deviation, etc. is dl, and the pattern deviation due to substrate shrinkage is Let the deviation be d2. Source electrode 80
1 and the semiconductor layer 803 for the drain electrode 802
The pattern deviation allowable dimension 808 is 2tL+ci or more. Further, the allowable pattern deviation dimensions 807, 809, 810, 811 of each of the gate t' 804, the source wiring 805, the drain wiring 806, and the semiconductor layer 803 with respect to the source electrode 801 and the drain electrode 1802 are d+ 10d2 or more. With the pattern deviation tolerance dimensions as described above, it is possible to eliminate variations in host capacitance even if pattern deviation occurs in any direction, and the semiconductor layer 803 is formed using polycrystalline silicon or the like at a high temperature of 500°C or higher. This is particularly effective when semiconductors are used.

The parasitic capacitance of the thin film transistor of the present invention and the parasitic capacitance of the conventional thin film transistor will be explained using FIG. 1st
FIG. 0(a) shows a top view of the thin film transistor of the present invention. The hatched areas SL and S indicate the gate voltage [!] using the gate insulating film as a dielectric. 1004 and source electrode 10
A parasitic capacitance is formed between 01 and 01. No matter which direction the pattern shift occurs, S1±S is constant, and its area is S, +33 = 2(Y2 (2a, Jushan/2) + W
/2 ・L/2 +W/2 (a, +d2))(
μ1) Y2 is the width of the source electrode 1001 (μm), L is the channel of the thin film transistor (μm), and W is the channel width of the thin film transistor (μm).

On the other hand, the gate voltage f! 1
A parasitic capacitance is formed between 004 and the drain electrode 1002, and its area is 32 =Y+ (2d+ +W/2 > +2 ・Wy
'2 ・L/'2 (lid) (2) Y is the drain electrode 1002! (μm).

Further, FIG. 10(b) shows a top view of a conventional thin film transistor. The gate electrode 10 is located in the area indicated by the shaded area S.
A parasitic capacitance is formed between 08 and the gate electrode 1005. Similarly, a parasitic capacitance is formed between the drain electrode 1006 and the gate electrode [1008] in the shaded portion S. If there is no pattern shift, the areas of S and S are equal, 34 = Ss = i2 (d+ +dz) +
W) (d+ +dz) +LW/2 (1d
It is expressed as l(3).

If the gate insulating films are made of the same material and have the same thickness, the parasitic capacitance is determined by the area 81 to S.

Here, the pattern deviation dl due to alignment accuracy, photomask pitch deviation, etc. is usually about 3 (μm).

Further, the shrinkage d2 of the substrate is approximately 6 μm per length l0C11 of the substrate, as shown in FIG. 6, at around 600'C, which is a general temperature for forming polycrystalline silicon.

Therefore, to equations (1), (2), and (3), dl-3, d2=0
．． Substituting 6X (X is the length of the substrate in the longitudinal direction (am)), we get S, +S, =2 (Yi (6W/2) +LW/
4+W/4 (3+O, (iX)) (μml (4) S2 =Y+ (6+W/2) 10LW/'2
(μml(5)S4=Ss=
(2(3+0.6X) 10W) (3+0.6X)±L
It becomes W/2 (6).

Compared to conventional thin film transistors, the parasitic capacitance formed between the source electrode and the gate electrode can be reduced by satisfying 31 +33 <34 (7).

Substituting equations (4) and (6) into equation (7) and rearranging it, we get Y2<2 <3+0.6X)'/(12+W)
[μml (8) is obtained.

That is, if the width Y2 of the source electrode satisfies equation (8), it becomes possible to reduce the parasitic capacitance formed between the source electrode and the gate electrode compared to conventional thin film transistors.

Figure 11 shows an equivalent circuit when applied to a liquid crystal display. The same number of parasitic capacitances 1106 as the gate wiring 1104 are formed in 1103, but since the parasitic capacitance 11o6 is small, the drive capacity of the hold circuit 1101 can be small, and the LSI can be made smaller and cheaper. Furthermore, a bold circuit with the same driving capability can drive a liquid crystal display with more gate wiring.

Compared to conventional thin film transistors, the parasitic capacitance formed between the drain electrode and the gate electrode can be reduced by satisfying 32<35 (9).

Substituting equations (5) and (6) into equation (9) and rearranging it, Yl<(6+1.2xW)(3+0.6X)/(6-1
-14/2) (If gol(10), that is, the width Y1 of the drain electrode satisfies equation (1o), the parasitic capacitance formed between the drain electrode and the gate electrode can be reduced compared to conventional thin film transistors. becomes possible.

Figure 12 shows a typical driving waveform for a liquid crystal display using thin film transistors. Figure 12 (a) is a gate signal applied to the gate wiring, which excites the thin film transistors in a time-divisional manner into a conductive state for each row. . Figure 12(b)
The data signal shown in is supplied to the source wiring in synchronization with the gate signal, and when the 6-gate signal is transmitted to the liquid crystal layer through the thin film transistor and transferred to the next row electrode, the thin film transistor becomes non-conductive and the source wiring and the liquid crystal layer are insulated. be done. Therefore, the data signal stored in the liquid crystal layer is held until the next scan. The voltage change in the liquid crystal layer is shown in FIG. 12(c), and a voltage change ΔV1201 occurs when the thin film transistor changes from a conductive state to a non-conductive state. This Δ■ is determined by the ratio of the parasitic capacitance JitC, formed between the drain electrode and gate electrode of the thin film transistor, and the liquid crystal MCLc, and is expressed by the following formula % Formula % In other words, if the parasitic capacitance &c p is smaller than that of a conventional thin film transistor, ΔV is It can be made smaller, has improved retention characteristics in the liquid crystal layer, is flicker-free, has a high contrast ratio, and can achieve high image quality. Furthermore, even if the liquid crystal display becomes larger, the parasitic capacitance does not change due to pattern deviation and can be made smaller, so a large liquid crystal display with high image quality can be realized.

When applied to image sensors and three-dimensional integrated circuits, the circuit constants are constant and can be brought closer to ideal values, making it possible to improve performance.

The characteristics of the thin film transistor of the present invention are shown in FIG. 8, where the horizontal axis represents the gate voltage V. 8. The vertical axis is the logarithm of the drain current 10. Drain voltage■. The 4(V) channel length is 20 μm and the channel width is 10 μm. Polycrystalline silicon is used for the semiconductor layer, and its thickness is 200 mm. As is clear from FIG. 8, both a small OFF current and a large ON current are compatible, and the characteristics are almost the same as those of conventional thin film transistors.

〔Effect of the invention〕

The present invention has the following excellent effects.

First, the parasitic capacitance formed between the source electrode and gate electrode of a thin film transistor can be smaller than that of a conventional thin film transistor, and when applied to a liquid crystal display, the load on the drive circuit is reduced, and the chip size is small and the driver is inexpensive. The IC becomes usable. If a driver IC with the same driving capability as the conventional one is used, it is possible to drive a liquid crystal display having even more scanning lines.

Second, the parasitic capacitance formed between the drain electrode and gate electrode of a thin film transistor can be made smaller than before, the signal voltage retention characteristics in the liquid crystal layer are improved, there is no flicker, and the contrast ratio is increased. High image quality is possible.

Third, even if the liquid crystal display becomes larger, there is no change in parasitic capacitance due to pattern deviation, so a large liquid crystal display with high image quality can be realized.

Fourth, the parasitic capacitance of the thin film transistor can be made constant regardless of pattern misalignment. This makes it possible to keep the circuit constants of an active matrix substrate using thin-film transistors or a logic circuit using thin-film transistors constant.

Fifth, by making circuit constants constant, it is possible to easily design an active matrix substrate or a logic circuit.

Sixth, since the design can be designed with a large tolerance to pattern deviations, the strict process control required in the past becomes unnecessary, and the yield is greatly improved.

Seventh, since the parasitic capacitance can be kept constant regardless of pattern misalignment, it is possible to eliminate variations within a substrate or between substrates, significantly improving quality, and even achieving uniform characteristics on large-area substrates. It is possible to realize the formation of thin film transistors.

Eighth, the transistor characteristics are exactly the same as the conventional characteristics, and both a small OFF current and a large ON current can be achieved.

Ninth, when using a semiconductor formed at a high temperature of 500°C or higher, such as polycrystalline silicon, for the semiconductor layer, it is possible to keep the parasitic capacitance constant without being affected by pattern shift caused by shrinkage of the substrate. This makes it possible to keep circuit constants constant.

As described above, the thin film transistor of the present invention has many excellent effects, and its application range is wide-ranging, including active matrix substrates for displays, peripheral circuits thereof, image sensors, and three-dimensional integrated circuits.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show the structure of a thin film transistor of the present invention, in which FIG. 1(a) is a top view and FIG. 1(b) is a sectional view. FIGS. 2(a) and 2(b) show the structure of a conventional thin film transistor, in which a) is a top view and FIG. 2(b) is a sectional view. FIGS. 3(a) to 3(c) are top views showing the structure of a conventional thin film transistor. FIG. 4 is an equivalent circuit diagram of a conventional thin film transistor. 5(a)-(e) and FIG. 8 are top views showing the structure of the thin film transistor of the present invention, and FIG. 6 is an equivalent circuit diagram! ! ! Figure 1. FIG. 7 is a graph showing shrinkage of the substrate. FIG. 9 is a graph showing the characteristics of the thin film transistor of the present invention. FIGS. 10(a) and 10(b) are top views of a thin film transistor of the present invention and a conventional thin film transistor. FIG. 11 is an equivalent circuit diagram of a liquid crystal display using thin film transistors. FIGS. 12(a) to 12(c) show driving waveforms of the liquid crystal display. 101.201...Substrate 103.202.301.503.801.1001.
1005... Source electrode 102.203.302
．． 502.802.1002.1006...Drain electrode 108.204.805...Source wiring 10
7.205.806...Drain wiring 104.206
．． 303.504.803.1003.1007...
...Semiconductor layer 105.207...Gate insulating film 106.208.304.506.804.1004
．． 1008...Gate electrode 401.402.60
1.602.603.1106... Parasitic capacitance 1101... Hold circuit 11
02・・・・・・・・・・・・Scanning circuits and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masayoshi Kamiyanagi (and 1 other person) (Fig. 5, Fig. 6, Fig. 7 - Nop υ Noρ 2ρ
30V, 5 (at VOρ) Figure 9 Figure 10 //N Figure 11

Claims (2)

[Claims] (1) On a predetermined substrate, a source electrode and a drain electrode, a semiconductor layer connecting the source electrode and the drain electrode, a gate insulating film covering the source electrode, the drain electrode, and the semiconductor layer, and the gate In a thin film transistor having a gate electrode provided through an insulating film, two source electrodes are wired in parallel to each other at a predetermined length with a predetermined line width at a predetermined interval; Between them, the line width Y_1 (μm) parallel to the two source electrodes is Y_1<(6+1.2X×W)(3+0.6X)/(6
+W/2) (μm)X is the length (cm) of the substrate in the longitudinal direction
) W satisfies the channel width (μm) of the thin film transistor,
A drain electrode wired to a predetermined length, the semiconductor layer provided in a direction intersecting the longitudinal direction of the two source electrodes and the drain electrode, and the semiconductor layer provided on the semiconductor layer via the gate insulating film. 1. A thin film transistor characterized in that it has a gate electrode that has a flat gate electrode. (2) The line width Y_2 (μm) of the two source electrodes is Y_
2. The thin film transistor according to claim 1, wherein the thin film transistor satisfies 2<2(3+0.6X)^2/(12+W) (μm).