JPH01267617A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To obtain the thin-film transistor which has no fluctuation in parasitic capacity by providing two pieces of drain electrodes wired in parallel to a prescribed length at a prescribed spaced interval and prescribed line width on an insulating substrate and source electrodes wired to a prescribed length at a prescribed line width. CONSTITUTION:This thin-film transistor has two pieces of the drain electrodes 102 wire din parallel to the prescribed length at the prescribed line width, the source electrode 103 wired to the prescribed length at the prescribed line width between the two drain electrodes 102, a semiconductor layer 104 provided in the direction intersecting with the longitudinal direction of the two drain electrodes 102 and the source electrode 103, a gate insulating film 105 which covers the drain electrodes 102, the source electrode 103 and the semiconductor layer 104, and a gate electrode 106 provided via the gate insulating film 105. The parasitic capacity of the thin-film TR is thereby kept always constant without being affected by a pattern deviation and the specified capacity of a piece of a source wiring 108 is obtd. as well. Namely, the delay time of signals does not fluctuate with each of the source wirings 108 and the liquid crystal display having the display quality uniform over a large screen and high image quality is obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor applied to active matrix liquid crystal displays, image sensors, three-dimensional integrated circuits, and the like.

[Conventional technology 1 Conventional thin film transistors are, for example, JAPAND ISP
The structure was as shown in P196-P199 of LAY'86, 1986. This structure is generalized and its outline is shown in FIG. (a) The figure is a top view, and (b) the figure is A.
It is a sectional view at A'. A source region 202 and a drain region 203 are formed on an insulating substrate 201 made of glass, quartz, sapphire, etc., which are made of a polycrystalline silicon thin film doped with impurities to serve as donors or acceptors. In contact with this, the source electrode 204 and the drain electrode 2
Further, a channel region 206 made of a polycrystalline silicon thin film is formed so as to touch and connect above the source region 202 and drain region 203. A gate insulating film 207 is provided to cover these. Furthermore, a gate electrode 208 is provided in contact with this.

[Problems to be Solved by the Invention] However, conventional thin film transistors have had the following problems.

FIG. 3 shows a front view of the thin film transistor, and FIG. 4 shows its equinodal circuit.

A parasitic capacitance J1401 is formed between the gate electrode 304 and the gate G and source S using the gate insulating film as a dielectric in the shaded area S1 shown in FIG. 3(a). Similarly, gate electrode 3
A parasitic capacitance 402 is formed between the gate G and the drain D at 04 and the shaded area S2.

As shown in FIG. 3(b), when a pattern shift of the gate electrode 304 occurs in the direction of an arrow 305, the parasitic capacitance 401 decreases and the parasitic capacitance 402 increases. On the contrary, Figure 3 (C)
As shown in FIG. 3, when a pattern shift of the gate electrode 304 occurs in the direction of the arrow 306, the parasitic capacitance 401 increases and the parasitic capacitance jt402 decreases. In other words, the parasitic capacitance of the thin film transistor is the source electrode 301 and the drain electrode 302.
The main cause of pattern deviation is the pattern deviation of the gate electrode 304.
misalignment, pitch misalignment between photomasks, etc. Therefore, parasitic capacitance varies within the same substrate or between substrates, making it difficult to keep circuit constants constant, and when applied to a liquid crystal display, display quality varies and image quality further deteriorates. Furthermore, as the size of the liquid crystal display increases, the pattern deviation becomes even larger, significantly degrading the display quality and becoming a major hindrance to increasing the size of the display.

When applied to image sensors and three-dimensional integrated circuits, it is difficult to maintain constant circuit constants, which has been a major hindrance to practical application.

The present invention is intended to solve these problems, and its purpose is to provide a thin film transistor with no variation in parasitic capacitance.

[Means for Solving the Problems 1] The thin film transistor of the present invention includes: (a) two drain electrodes wired in parallel on an insulating substrate at a predetermined distance and having a predetermined line width and a predetermined length; a source electrode wired between the two drain electrodes with a predetermined line width and a predetermined length; a semiconductor layer provided in a direction intersecting the longitudinal direction of the two drain electrodes and the source electrode; The semiconductor device is characterized by comprising a gate insulating film covering the drain electrode, the source electrode, and the semiconductor layer, and a gate electrode provided through the gate insulating film.

(b) The line width y1 (μm) of the source electrode is y +
< (6+1.2x+Wl f3+0.6x)
/ (6+W/2) (umlX is the length (μm) of the insulating substrate in the longitudinal direction, and W satisfies the channel width (μm) of the thin film transistor.

(C) The line width ya (μm) of the two drain electrodes is y! < 2 (3+0.6xl”/ (12+W
) (μm).

[Example 1] The present invention will be described in detail based on Examples below. 1st
An example of a thin film transistor according to the present invention is shown in the figure (a
) is a front view, and (b) is a sectional view at BB'. On an insulating substrate 101 made of glass, quartz, sapphire, etc., two drain electrodes 102 made of silicon thin films such as polycrystalline silicon, amorphous silicon, etc. doped with impurities to serve as donors or acceptors are provided in parallel to each other. ing. A source electrode 103 is made of the same material as the drain electrodes and is provided between two drain electrodes 102 so as to be parallel to the drain electrodes 102 . In addition, the line width of the source electrode 103 and the drain electrode 102 is preferably 20 μm or less, and the film thickness is preferably 500 to 5000 μm. Semiconductor layer 1 made of a silicon thin film such as polycrystalline silicon or amorphous silicon
04 is formed. The film thickness is preferably 2000 Å or less, and the source wiring 1 is made of metal, transparent conductive film, etc.
08 is in contact with the source electrode lO3, and similarly, the drain wiring 107 is in contact with the two drains i[1fi102. A gate insulating film 105 of SiO□, 5iON, etc. covers all of these. On top of this, a gate electrode 106 made of metal, transparent conductive film, etc. is placed on the gate insulation 1 [1105
The semiconductor layer 104 is coated via the semiconductor layer 104. Gate insulation lit 05 is an interlayer that maintains insulation between wiring! lPa
It also serves as A thin film transistor configured in this manner is equivalent to two thin film transistors connected in parallel. The channel length of the thin film transistor is indicated by an arrow 109 in FIG. 1, and the distance between the two parallel drain electrodes 102 is twice the channel length plus the line width of the source electrode 103. Also, the channel width W is twice the value indicated by arrow 110.

FIG. 5 shows a top view of the thin film transistor of the present invention, and FIG. 6 shows its equivalent circuit.

Parasitic capacitances 601 and 602 are formed between the gate G and the drain D using the gate insulating film as a dielectric between the gate electrode 506 and the hatched areas S and S shown in FIG. 5(a). Similarly, a parasitic capacitance 603 is formed between the gate G and the source S at the gate electrode 506 and the shaded area S4. As shown in FIG. 5(b), even if the pattern of the gate electrode 506 is misaligned in the direction of the arrow 511, the areas of Sl, S4, and Ss remain constant without changing at all, and as a result, the parasitic capacitance 601. 60
No. 2,603 is not affected by pattern deviation at all and remains constant. Further, the same problem occurs even if the pattern of the gate electrode 506 is misaligned in the direction of the arrow 512 as shown in FIG. 5(C).

When a pattern shift occurs in the direction shown in FIG. 5(d), the area of S4 is the same as when there is no pattern shift, but the areas of S8 and S change. In other words, the parasitic capacity is 60
1 becomes larger and 602 becomes smaller, but as is clear from the equivalent circuit shown in Figure 6, the parasitic capacitances 601 and 602 are in parallel, so the total parasitic capacitance on the drain side is different from that when there is no pattern shift. Same (s s + s
y = s ) + s a ).

The case of Fig. 5(e) is exactly the same (SIl+S@”S s
+ S s ) is 0 or more As explained above, the parasitic capacitance of the thin film transistor is always constant no matter which direction the pattern shift occurs. That is, it is possible to eliminate variations in parasitic capacitance within the same substrate or between substrates.

Glass substrates are widely used as insulating substrates for forming thin film transistors. Generally, when a glass substrate is heat-treated and returned to room temperature, the dimensions after the heat treatment become smaller than the dimensions of the glass before the heat treatment.

(Hereinafter referred to as substrate shrinkage) As an example, FIG. 7 shows the shrinkage of a #7059 (manufactured by Corning) substrate, where the horizontal axis shows the heat treatment temperature and the vertical axis shows the amount of substrate shrinkage per 10 cm.
As is clear from FIG. 7, heat treatment at 500° C. or higher causes rapid shrinkage of the substrate. When the semiconductor layer 504 is made of a semiconductor formed at a high temperature of 500° C. or higher, such as polycrystalline silicon, the substrate shrinks after the semiconductor is formed, causing the drain electrode 50 to shrink.
The pattern deviation of the semiconductor layer 504 and the gate electrode 506 with respect to the semiconductor layer 504 and the source electrode 502 becomes large. This will be explained using FIG. A source electrode 801 and a drain electrode 802 are formed, and after patterning into the shape shown in FIG. 8, a semiconductor layer 803 is formed. When forming the semiconductor layer 803, shrinkage of the substrate occurs. Therefore, the semiconductor layer 803,
The pattern deviation of the gate electrode 804, the source wiring 805, and the drain wiring 8.6 must take into account the shrinkage of the substrate.Here, let d be the pattern deviation due to alignment accuracy, photomask pitch deviation, etc., and let d be the pattern deviation caused by the shrinkage of the substrate. Let the pattern deviation be d2. The allowable pattern deviation dimension 808 of the semiconductor layer 803 with respect to the source electrode 801 and the drain electrode 802 is set to be 2d + +d i or more. Also, a gate electrode 804 for the source electrode 801 and the drain electrode 802. The allowable pattern deviation dimensions 807.809.810.811 of each of the source wiring 805, -drain wiring 806, and semiconductor layer 803 are d l + d
If the allowable dimension of pattern deviation is set to x or more, such as 0 or more, it is possible to eliminate variations in parasitic capacitance even if pattern deviation occurs in any direction. This is particularly effective when using semiconductors formed at high temperatures.

The parasitic capacitance of the thin film transistor of the present invention and the parasitic capacitance of the conventional thin film transistor will be explained using FIG. 1O. 1st
Figure O (a) shows a top view of the thin film transistor of the present invention. The hatched areas SI and S indicate the gate electrode 1004 and the drain electrode 1004 using the gate insulating film as a dielectric.
A parasitic capacitance is formed between 02 and 02. Sl + Ss is constant no matter which direction the pattern shift occurs, and its area is: Sl + Ss・2(yi(2d++W/2)+W/2・L
/2+W/2(dl+da)1(μm')-(1) y2 is the width of the drain electrode 1002 (μm) L is the channel length of the thin film transistor (μm) W is the channel width of the thin film transistor (μm).

On the other hand, the gate electrode 10 is
A parasitic capacitance is formed between 04 and the source electrode 1001, and its area is S z”y+ (2d++W/21 +24/2・L/
2 (μm″) −(2) y is expressed by the radius of the source electrode 1001 (μm).

Further, FIG. 10(b) shows a top view of a conventional thin film transistor, and the gate electrode 10 is
Similarly, a parasitic capacitance is formed between the drain electrode 1006 and the gate electrode 1008 at the portion shown by the diagonal line S5 where a parasitic capacitance is formed between the drain electrode 1006 and the source electrode 1005. If there is no pattern shift, the areas of S4 and 86 are equal, S a =S i = (2(d++dil+W)
(d++d*)+LW/2(urn”) −(3
).

If the gate insulating films are made of the same material and have the same thickness, the parasitic capacitance is proportional to the area 51 to Ss.

Here, the pattern deviation d due to alignment accuracy, photomask pitch deviation, etc. is usually about 3 (μm).

Further, the shrinkage d of the substrate is about 6 μm per 10 cm of the length of the substrate at around 600° C., which is a general temperature for forming polycrystalline silicon, as shown in FIG.

Therefore, to equations (1), (2), and (3), d = 3゜d*
=0.6x (x is the length in the longitudinal direction of the substrate (Cffi
)), we get S, + S! = 2(yi(6+W/2)+L
W/4+W/2(3+0.6xll(μrrI'')-(
4) S z = y + (6+ W / 2) +
L W / 2 (μm)" - (5) S 4 + S s = (2 (3 + a, 6xl + Wl
(3+0.6x)+LW/2.

In order to reduce the parasitic capacitance formed between the source electrode and the gate electrode compared to conventional thin film transistors, it is sufficient to satisfy S2<34-(7).

Substituting equations (4) and (6) into equation (7) and rearranging, y , < (6+1.2x+W) (3+0.6x
l/(6+W/21(μm)−(8)) is obtained.

That is, if the width y1 of the source electrode satisfies equation (8), it is possible to reduce the parasitic capacitance formed between the source electrode and the gate electrode compared to conventional thin film transistors.

FIG. 11 shows an equivalent circuit when applied to a liquid crystal display. In one source wiring 1103, the same number of parasitic capacitances 1106 as gate wirings 1104 are formed.

The width y of the source electrode is the line width of the mask alignment resolution βi4, N S R-L 750/G
If (B optical system) is used, 4 (+1 m) becomes possible t12. 17 Items: 10 pieces of yarn length
(um), channel re W is 10 (gm) t]ge S,
is 94 (um'), and in the conventional :ll11-transistor, the length in the longitudinal direction of the substrate is 7! -30 (cm) and Jl is 114? , (um'), and the area S 4 / S 2 is approximately 12, which is compared to the conventional 4-film i
・5 raw volumes jtl106 given to a transistor will be 1/12. General (When performing this TV L failure, gate wiring 110
4 is about 500 lines, so one source line is 110 lines.
3, the parasitic capacitance is 1/6000, and the drive capacity of the hold circuit 1101 is 1/600 compared to the conventional one.
0, which can be significantly reduced. Therefore, the LSi can be made smaller and at the same time cheaper. Also, parasitic capacitance 1006
is always constant without being affected by pattern deviation, so the capacitance of one source wire remains unchanged and the load on the hold circuit 1oot also remains constant. As a result, there is no variation in the signal delay time for each source wiring, and a high-definition liquid crystal display with uniform display quality across the large screen. realizable.

Compared to conventional thin film transistors, the drain electrode and
To reduce the parasitic capacitance formed between one pole, S + + S s < S s
It is sufficient if (9) is satisfied.

Substituting equations (5) and (6) into equation (9) and sorting it out, we get y! <2 (3+056x)”/ (12+W)(μ
m) - (10) In other words, if the width y2 of the drain electrode satisfies the equation (lO), it is possible to reduce the parasitic capacitance formed between the drain electrode and the gate electrode compared to conventional thin film transistors. .

Figure 12 shows a typical driving waveform for a liquid crystal display using thin film transistors. Figure 12 (a) is a gate signal applied to the gate wiring, which excites the thin film transistors in a time-divisional manner into a conductive state for each row. . Figure 12(b)
The data signal shown in is supplied to the source line in synchronization with the gate signal.

It is transmitted to the liquid crystal layer through a thin film transistor.

When the gate signal is transferred to the next row electrode, the transistor becomes non-conductive, and the source wiring and the liquid crystal layer are insulated. Therefore, the data signals applied to the liquid crystal layer are held until the next scan. The voltage change in the liquid crystal layer is shown in FIG. 12(e). When the thin film transistor changes from a conductive state to a non-conductive state, a voltage change ΔV1201 occurs. This 8V is a thin film transistor, 2. It is determined by the ratio of the parasitic capacitance fftcp formed between the drain electrode and gate electrode of the liquid crystal layer and the liquid crystal layer Ctc, and is expressed by the following equation.

ΔVOCCp/Cp+CLc That is, if the parasitic capacitance 1tcp is smaller than that of a conventional thin film transistor, ΔV can be reduced, the retention characteristics in the liquid crystal layer are improved, there is no flicker, the contrast ratio is increased, and high image quality can be achieved. Furthermore, even if the liquid crystal display becomes larger, the parasitic capacitance does not change due to pattern misalignment and can be made smaller, making it possible to see a large liquid crystal display with high image quality.

The characteristics of the thin film and transistor of the present invention are shown in FIG. 9, where the horizontal axis is the gate voltage Vos and the vertical axis is the drain current 1. is the logarithm of The drain voltage VD is 4 (■), the channel length is 20 th m, and the channel width is 10 μm. Polycrystalline silicon is used for the semiconductor layer, and its thickness is 200 mm. As is clear from FIG. 8, a small 0FFif current and a large 0Ntit current are compatible, and the characteristics are almost the same as those of conventional thin film transistors.

[Effect of the invention] The present invention has the following excellent effects.

First, it is possible to always keep the parasitic capacitance of thin film transistors constant without being affected by pattern misalignment.
As a result, the capacitance of one source line also becomes constant. In other words, it is possible to realize a screen-quality liquid crystal display with uniform display quality over a large screen without variations in signal delay time for each source wiring.

Second, the parasitic capacitance formed between the source electrode and gate electrode of a thin film transistor can be smaller than that of conventional thin film transistors, and when applied to liquid crystal displays, the load on the drive circuit is reduced, and the chip size is small and inexpensive. driver IC can be used. If a driver IC with the same driving capability as the conventional one is used, it is possible to drive a liquid crystal display having even more scanning lines.

Third, the parasitic capacitance formed between the drain electrode and gate electrode of a thin film transistor is not affected by pattern misalignment, is constant, and is smaller than before (this makes it possible to improve the signal voltage retention characteristics in the liquid crystal layer). , no flicker,
The contrast ratio increases, allowing for higher image quality.

Fourth, by making the circuit constant constant, it is possible to easily design an active matrix substrate or a hold circuit.

Fifth, since the design can be designed with a large tolerance to pattern deviations, the strict process control required in the past becomes unnecessary, and the yield is greatly improved.

Sixth, since the parasitic capacitance can be kept constant regardless of pattern misalignment, it is possible to eliminate variations within a substrate or between substrates, greatly improving quality, and even achieving uniform characteristics on large-area substrates. It is possible to realize the formation of thin film transistors.

Seventh, the transistor characteristics are exactly the same as the conventional characteristics, and both a small OFF current and a large ON current can be achieved.

Eighth, when a semiconductor formed at a high temperature of 500°C or higher, such as polycrystalline silicon, is used for the semiconductor layer, it is possible to maintain a constant parasitic capacitance without being affected by pattern shift caused by shrinkage of the substrate. This makes it possible to keep circuit constants constant.

As described above, the thin film transistor of the present invention has many excellent effects, and its application range is wide-ranging, including active matrix substrates for displays, peripheral circuits thereof, image sensors, and three-dimensional integrated circuits.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show the structure of a thin film transistor of the present invention, in which FIG. 1(a) is a top view and FIG. 1(b) is a sectional view. FIGS. 2(a) and 2(b) show the structure of a conventional thin film transistor, in which a) is a top view and FIG. 2(b) is a sectional view. FIGS. 3(a) to 3(C) are top views showing the structure of a conventional thin film transistor. FIG. 4 is an equivalent circuit diagram of a conventional thin film transistor. 5(a)-(e) and FIG. 8 are top views showing the structure of the thin film transistor of the present invention, and FIG. 6 is an equivalent circuit diagram. FIG. 7 is a graph showing shrinkage of the substrate. FIG. 9 is a graph showing the characteristics of the thin film transistor of the present invention. FIGS. 1A and 1B are top views of a thin film transistor of the present invention and a conventional thin film transistor. FIG. 11 is an equivalent circuit diagram of a liquid crystal display using thin film transistors, and FIGS. 12(a) to (C) are driving waveforms of the liquid crystal display. 101.201... Board 103.202.301.502.801, fool,
1005... Source electrode 102, 203, 302
,503,802.1002.1006...Drain electrode 108.204.805...Source wiring 1
07.205.806...Drain wiring 104.20
6.303.504.803.1003.1007...
...Semiconductor layer 105.207...Gate insulating film 106.208, 304, 506.804.100
4.1008...Gate electrode 401.402,6
01,602,603.1106・・・・・・・・・・
Parasitic capacitance 1101...Hold circuit 1
102......Scanning circuit 1103...
...Source wiring 1104...
Gate wiring 1107......LCD 1 Applicant: Seiko Epson Co., Ltd. Agent Patent attorney Masataka Ueyanagi (and 1 other person) (Fig. 1 (H) Cb) Fig. 2 p4 Figure 3<C) Fifth! ! I β no E) cr Fig. 6 300 460! ;DOlρD7ρ0 drawing card
(d) Ichino ρ D 1
0 2ρ 30Vc
Ts (VolL) Figure 9 1oo Figure 10

Claims (3)

[Claims] (1) With a predetermined line width at a predetermined interval on an insulating substrate,
Two drain electrodes wired in parallel to a predetermined length,
A source electrode wired between the two drain electrodes with a predetermined line width and a predetermined length parallel to the two drain electrodes, and a source electrode wired in a longitudinal direction of the two drain electrodes and the source electrode. A thin film transistor comprising semiconductor layers provided in intersecting directions, a gate insulating film covering the drain electrode, the source electrode, and the semiconductor layer, and a gate electrode provided through the gate insulating film. . (2) The line width y_1 (μm) of the source electrode is y_1<(
6+1.2_x+W)(3+0.6_x)/(6+W/
2) (μm) The thin film transistor according to item 1, wherein x is the length in the longitudinal direction of the insulating substrate (μm), and W satisfies the channel width (μm) of the thin film transistor. (3) The line width y_2 (μm) of the two drain electrodes is y_2<2(3+0.6_x)^2/(12+W)(μ
2. The thin film transistor according to item 1, which satisfies m).