JPH0279476A - Film type transistor - Google Patents

Abstract

PURPOSE:To provide a film type transistor without variations of parasitic capacitance by furnishing two drain electrodes arranged apart at a certain distance, a source electrode wired between these electrodes, and a wiring tying the two drain electrodes. CONSTITUTION:Two drain electrodes 103 consisting of silicon film, to which impurity to become doner or acceptor is added, are provided on an insulating substrate 101 of glass, quartz, sapphire, etc. A source electrode 102 in the same material as electrode 103 is furnished between the two electrodes 103. A semiconductor layer 104 consisting of silicon film is formed on a line tying the two drain electrodes 103 and source electrodes 102 in contact with their overside, and these are covered with a gate insulation film 105, and thereon a gate electrode 16 is furnished. Further a contact hole 108 is provided on the electrodes 103, and a drain wiring 107 is formed from metal, etc., so that the potentials of the two drain electrodes 103 become equal. Thereby a film type transistor with the parasitic capacitance held constant is obtained irrespective of dislocation of the pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor applied to active matrix liquid crystal displays, image sensors, three-dimensional integrated circuits, and the like.

[Conventional technology]

Conventional thin film transistors are, for example, JAPANDISP
The structure was as shown in pages 196 to 199 of LAY '86, 1986. This structure is generalized and its outline is shown in Figure 2. Figure (a) is a top view;
b) The figure is a sectional view at AA'. glass, quartz,
On an insulating substrate 201 such as sapphire, a donor or
A source region 202 and a drain region 203 are formed of a polycrystalline silicon thin film doped with impurities to serve as acceptors. A source electrode 204 and a drain electrode 205 are provided in contact with this, and a source region 20
A channel region 20B made of a polycrystalline silicon thin film is formed so as to contact and connect the drain region 2 and the drain region 203 above. Gate insulation WA to cover these
207 is provided. Furthermore, in contact with this, a gate electrode 2
08 is provided.

[Problem to be solved by the invention]

However, conventional thin film transistors have the following problems.

FIG. 3 shows a top view of the thin film transistor, and FIG. 4 shows its equivalent circuit.

A parasitic capacitance ff1401 is formed between the gate electrode 304 and the gate G and source S using the gate insulating film as a galvanic body in the shaded area S1 shown in FIG. 3(a). Similarly, a parasitic capacitance 402 is formed between the gate G and the drain D at the gate electrode 304 and the hatched portion S2.

As shown in FIG. 3(b), when a pattern shift of the gate voltage 304 occurs in the direction of an arrow 305, the parasitic capacitance 401 decreases and the parasitic capacitance 402 increases. On the contrary, Figure 3 (C)
As shown in FIG. 3, when a pattern shift of the gate electrode 304 occurs in the direction of the arrow 306, the parasitic capacitance 3t401 increases and the parasitic capacitance ff1402 decreases. In other words, the parasitic capacitance of a thin film transistor varies greatly due to pattern misalignment of the gate electrode 304 with respect to the source electrode 301 and the drain electrode 302.
04 alignment deviation, pitch deviation between photomasks, etc. Therefore, parasitic capacitance varies within the same substrate or between substrates, making it difficult to keep circuit constants constant, and when applied to a liquid crystal display, display quality varies and image quality further deteriorates. Furthermore, as the size of the liquid crystal display increases, the pattern deviation becomes even larger, significantly degrading the display quality and becoming a major hindrance to increasing the size of the display.

When applied to image sensors and three-dimensional integrated circuits, it is difficult to maintain constant circuit constants, which has been a major hindrance to practical application.

The present invention solves these problems, and its purpose is to provide a thin film transistor with no variation in parasitic capacitance. , comprising two drain electrodes spaced apart from each other by a predetermined distance, a source electrode wired between the two drain electrodes, and a wire connecting the two drain electrodes.

〔Example〕

The present invention will be described in detail below based on Examples.

FIG. 1 shows an example of a thin film transistor according to the present invention.

(a) is a top view, and (b) is a cross-sectional view at BB'. Insulating substrate 1 made of glass, quartz, sapphire, etc.
Two drain electrodes 103 made of silicon thin films such as polycrystalline silicon or amorphous silicon doped with impurities to serve as donors or acceptors are provided on the drain electrode 01.

A source electrode 102 is provided between two drain electrodes 103 made of the same material as the drain electrodes. The film thickness is 5
00-5000A is desirable. The source electrode 102 is made of metal, a conductive film such as a transparent conductive film, or
The surface of these conductive electrodes may be covered with the same material as the drain electrode to have a two-layer structure. Polycrystalline silicon or amorphous silicon may be used so as to touch and connect the upper sides of the two drain electrodes 103 and source electrodes 102. A semiconductor layer 104 made of a silicon thin film is formed. The film thickness is 200
0A or less is desirable, and the whole is SiO2 + 5iNx
It is covered with a gate insulating film 105 such as S5iON.

On top of this, a gate electrode 10 made of metal, transparent conductive film, etc.
6 is provided. Further, a contact hole 108 is provided on the drain electrode 103, and a drain wiring 107 is formed of metal or a transparent conductive film so that the potentials of the two drain electrodes 103 are equalized. The gate electrode 106 and the drain wiring 107 may be formed of the same material at the same time.

A thin film transistor configured in this manner is equivalent to two thin film transistors connected in parallel. The channel length of the NI film transistor is indicated by arrow 109 in FIG. 1, and the channel width W is twice the value indicated by arrow 110.

FIG. 5 shows a main perspective view of the thin film transistor of the present invention.
The equivalent circuit is shown in the figure.

The gate electrode 506 and the gate G and source S are connected using the gate insulating film as a current collector at the hatched areas S3 and S5 shown in FIG. 5(a).
Parasitic capacitances ff1601 and 802 are formed between them.

Similarly, a parasitic capacitance 603 is formed between the gate G and the drain D at the gate electrode 506 and the shaded area S4. Figure 5 (b
), when a pattern shift occurs in the direction of arrow 511, the area of S4 is the same as when there is no pattern shift, but the area of S5 changes by 83 degrees. In other words, it is parasitic!
601 becomes larger and 602 becomes smaller, but as is clear from the equivalent circuit shown in Fig. 6, since the parasitic capacitances ff1601 and 602 are in parallel, the total parasitic capacitance on the source side is the same as when there is no pattern shift. Same (S@+S?
=33+S device). The case of FIG. 5(C) is exactly the same (S reference + S *= S s + S s).

As explained above, the parasitic capacitance of the thin film transistor is always constant no matter in which direction pattern deviation occurs.

That is, it is possible to eliminate variations in parasitic capacitance within the same substrate or between substrates.

Glass substrates are widely used as insulating substrates for forming thin film transistors. Generally, glass substrates are heat treated,
When the temperature is returned to room temperature, the dimensions of the glass after heat treatment become smaller than those before heat treatment.

(Hereinafter referred to as substrate shrinkage) As an example, FIG. 7 shows the shrinkage of a #7059 (manufactured by Corning) substrate, where the horizontal axis shows the heat treatment temperature and the vertical axis shows the amount of substrate shrinkage per 10 cm.
As is clear from FIG. 7, heat treatment at 500° C. or higher causes rapid shrinkage of the substrate. This is particularly effective when the semiconductor layer 504 uses a semiconductor formed at a high temperature of 500° C. or higher, such as polycrystalline silicon. Further, even if the substrate shrinks, it is possible to keep the circuit constant constant, and when applied to a liquid crystal display, there is no variation in display quality, and image quality can be significantly improved. Furthermore, since the source electrode can be formed below the drain wiring, that is, the pixel electrode, there is no need to provide a space for forming the source electrode between the pixel electrodes, so that the aperture ratio can be increased.

〔Effect of the invention〕

The present invention has the following excellent effects.

First, the parasitic capacitance of the thin film transistor can be kept constant regardless of the direction of pattern deviation, and when used in an active matrix type liquid crystal display,
Large area and high image quality can be achieved at the same time.

Second, by making circuit constants constant, it is possible to easily design an active matrix substrate or a logic circuit.

Third, since the design can be designed with a large tolerance to pattern deviations, the strict process control required in the past becomes unnecessary, and the yield is greatly improved.

Fourth, when used in a liquid crystal display, the source electrode can be formed below the pixel electrode, so the pixel electrode can be made larger, resulting in a bright screen with a large aperture ratio.

Fifth, the alignment of the liquid crystal is not disturbed due to the potential difference between the source electrode and the pixel electrode, and high image quality can be achieved.

Sixth, since the parasitic capacitance can be kept constant regardless of pattern misalignment, it is possible to eliminate variations within a substrate or between substrates, greatly improving quality, and even achieving uniform characteristics on large-area substrates. It is possible to realize the formation of thin film transistors.

Seventh, when a semiconductor formed at a high temperature of 500°C or higher, such as polycrystalline silicon, is used for the semiconductor layer, it is possible to maintain a constant parasitic capacitance without being affected by pattern shift caused by shrinkage of the substrate. This makes it possible to keep circuit constants constant.

As described above, the thin film transistor of the present invention has many excellent effects, and its application range is wide-ranging, including active matrix substrates for displays, peripheral circuits thereof, image sensors, and three-dimensional integrated circuits.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show the structure of a thin film transistor of the present invention, where (a) is a main view and (b) is a cross-sectional view. FIGS. 2(a) and 2(b) show the structure of a conventional thin film transistor, in which a) is a top view and FIG. 2(b) is a sectional view. FIGS. 3(a) to 3(c) are top views showing the structure of a conventional thin film transistor. FIG. 4 is an equivalent circuit diagram of a conventional thin film one-herald transistor. 5(a) to 5(C) are top views showing the structure of the thin film transistor of the present invention, and FIG. 6 is an equivalent circuit diagram. FIG. 7 is a graph showing shrinkage of the substrate. 101.201... Substrate 102.202, 301, 503... Source electrode 103, 203. 302. 502...Drain electrode 204...Source wiring 107.205...Drain wiring 104.206, 303, 504...Semiconductor layer 105
．． 207... Gate insulating film 106. 208, 304, 506... Gate electrode 401, 402. 601. 802. 603...
・More than parasitic capacitance Applicant Seiko Epson Co., Ltd. agent Patent attorney Upper column Masayoshi and 1 other person $1 Figure (Yun<b) Figure 2 Figure 4, SQ Figure 6

Claims (3)

[Claims] (1) On a predetermined substrate, a source electrode and a drain electrode, a semiconductor layer connecting the source electrode and the drain electrode, a gate insulating film covering the source electrode, the drain electrode, and the semiconductor layer, and the gate In a thin film transistor including a gate electrode provided through an insulating film, two drain electrodes are provided at a predetermined interval, a source electrode is wired between the two drain electrodes, and the two drain electrodes are provided at a predetermined interval. A thin film transistor characterized by being equipped with wiring that connects to an electrode. (2) The thin film transistor according to claim 1, wherein the two drain electrodes and the source electrode are formed at the same time. (3) The thin film transistor according to claim 1, wherein a wiring connecting the gate electrode and the two drain electrodes is formed at the same time.