JPH01246863A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a CMOS structure not using an ion implantation device by a method wherein the deposition method is employed to form a dopantintroduced semiconductor thin film. CONSTITUTION:An N-type Si thin film is attached to an insulating substrate 1 using the deposition method and is formed into islands using photolithography for the construction of N-channel field effect type thin film transistor drain electrode 2 and source electrode 3. A channel section 4 is formed of a dopant- free semiconductor thin film, a gate insulating film 5 is positioned on the channel section 4, and a gate electrode 6 is built over the channel section 4. Another gate insulating film 7 is formed on the gate electrode 6, and a P-channel field effect type thin film transistor drain electrode 8 and source electrode 9 are built on the gate insulating film 7. A channel section 10 is formed of a dopant- free semiconductor thin film bridging the two electrodes 8 and 9. A CMOS inverter is constructed when connection is established by a metal wire 13 and others among the electrodes. In this way, a CMOS structure may be built without an ion implantation device.

Description

[Detailed Description of the Invention] [Industrial Application Field 1] The present invention is applicable to flat displays such as liquid crystal displays and electrochromic displays, image sensors, and SOI devices.
The present invention relates to a semiconductor device used in a device such as an ulator, and a method for manufacturing the same.

[Prior art] Conventionally, for example, a conference record
f the1985 International D
isplayRe5earchConference
, P. 9-13 (1985), it has been common to use ion implantation as a method for forming a CMO5 structure (complementary MO3 structure) on an insulating substrate.

[Problem B to be Solved by the Invention] However, in the above-mentioned conventional technology, the dopant is introduced using an ion implantation method, so it is essential to use an expensive ion implantation device, and the processing capacity is also small.

Furthermore, since it is necessary to maintain the temperature at a high temperature in order to activate the dopant after ion implantation, it has the disadvantage that expensive quartz glass must be used as the insulating substrate.

In addition, since the elements are formed on an insulating substrate, CM
The parasitic capacitance between the power supply electrodes of an OS element, such as an impark (inverting amplifier), is small and is susceptible to electrical noise. Furthermore, creating a new capacitive element for this purpose lowers the degree of integration of the element and complicates the process.

Therefore, the present invention is intended to solve the above-mentioned drawbacks.The purpose of the present invention is to make it possible to use an inexpensive glass substrate as an insulating substrate, to form it by a manufacturing method that is suitable for mass production, and to reduce electrical noise. The point is that it provides a strong CMO3 structure.

Another object is to provide a reliable manufacturing method for achieving the above object.

[Means for Solving the Problems 1 (1) In the semiconductor device of the present invention, an N-channel field-effect thin film transistor and a P-channel field-effect thin film transistor disposed on an insulating substrate share a gate electrode, and at least one of them shares a gate electrode. It is characterized by including a structure configured such that the parts overlap.

(2) The manufacturing method of the present invention includes a low pressure CVD method, an ordinary pressure CVD method, and a plasma CVD method as a film forming method for forming an N-type semiconductor thin film and a P-type semiconductor thin film that are constituent elements of the semiconductor device described in item 1. It is characterized by using a deposition method such as

[Embodiment] FIG. 1 shows an impark (inverting amplifier) as an embodiment using the structure and manufacturing method according to the present invention.
(a) is a top view, and (b) is a sectional view taken along line AA' in (a).

A drain electrode part 2 and a source electrode part 3 of an N-channel field effect thin film transistor (NchTFT) made of an N-type semiconductor are formed on an insulating substrate l. A channel section 4 is formed of a semiconductor thin film containing no dopant so as to connect between the picture electrode sections 2 and 3. A gate insulating film 5 is formed on top of it, and further on top of it,
A gate electrode 6 made of an N-type or P-type semiconductor or a high-melting point metal is formed. Furthermore, a gate insulating film 7 different from the gate insulating film described above is formed on top of the gate insulating film.

A drain electrode portion 8 of a P-channel field effect thin film transistor (PchTFT) made of a P-type semiconductor is disposed on the top thereof.
and a source electrode portion 9 are formed, and a channel portion lO is formed of a semiconductor thin film containing no dopant so as to connect between the picture electrodes 8 and 9. Metal wiring 12.13.14.1
A CMOS inverter is constructed by connecting each electrode through a contact hole 11.

The feature of the structure of the CMOS Impark according to the present invention is that the gate electrode part 6 is TPT of both Nch TFT and Pch TFT.
This is the point where the gate electrode is used.

Another feature is that the source electrode part 3 of the Nch TFT and the Pch
TFT source electrode section 9 and two gate insulating films 5.7
The point is that a capacity consisting of is created.

1 of the manufacturing process of a semiconductor device having the structure shown in Fig. 1
A portion of an example is shown in FIG. 2 and will be described in more detail.

First, an N-type S1 thin film is deposited on an insulating substrate 1 using a deposition method such as a low pressure CVD method, an ordinary pressure CVD method, or a plasma CVD method, and the thin film is processed into an island shape using a photolithography method. A drain electrode portion 2 and a source electrode portion 3 are formed. (Fig. 2a) Next, in order to form the channel part 4 of the Nch TFT,
Using the above deposition method, dopant-free S
i Deposit the thin film and use photolithography method.

(FIG. 2b) Next, a SiO2 film which will become the gate insulating film 5 is formed using the deposition method described above. Furthermore, an N-type Si thin film or a P-type SiR film is deposited using the above deposition method, or a high-melting point metal such as Cr, Co, Mo, Ni, Ta, Ti, W, or silicide is deposited by a sputtering method or the like. Then, a gate electrode 6 is formed using a photolithography method. (FIG. 2C) An Nch TFT is constructed through the above steps. A PchTFT is constructed in the following steps, and a feature of the present invention is that the gate electrode 6 formed in the previous step (C) serves as the gate electrode of the PchTFT that is constructed in the following steps.

First, the gate insulating film 7 is formed by the deposition method on the Nch TFT manufactured in the steps (a) to (c).

(Fig. 2 d) Next, a P-type Si thin film is deposited using the deposition method, and the thin film is processed using a photolithography method.
A drain electrode portion 8 and a source electrode portion 9 of the chTFT are formed. (FIG. 2e) The insulating film 7 formed in the previous step plays the following role in this step.

(I) When depositing a P-type Si thin film using the above deposition method, a P-type dopant is added to the N-type Si thin film.
It functions to prevent interdiffusion of N-type dopants in the Si thin film, and the N-type Si thin film and P-type S dopant due to interdiffusion.
It becomes possible to prevent the resistance of the i-thin film from increasing.

(II) When processing a P-type Si thin film by photolithography, it acts as an etching stopper, making it possible to perform stable etching over the entire surface of a large-area substrate.

(Ill) One of the reasons for using a glass substrate is that it is easy to increase the area of the substrate, but due to the effects of (I) and (II), TPT can be stably formed over a large area. It becomes possible to use a glass substrate.

The source electrode portion 9 formed in FIG. 2e, the source electrode portion 3 formed in FIG. 2a, and the two gate insulating films 5.7
The capacity is made up of:

In the next step, the dopant-free Si thin film deposited using the deposition method is processed using the photolithography method to obtain the channel portion 10.
FT is also configured.

NchT F' with a common gate electrode in the above process
Wiring 12.13 made by forming a contact hole 11 at a predetermined position in the 0th order where T and Pch TFTs are formed by photolithography, and then processing a metal thin film deposited by sputtering by photolithography.
．． NchTFT and PchTF by forming 14
T is electrically formed to obtain the inverter shown in FIG.

In addition, in the above manufacturing process, the PchTFT is replaced by the NchTFT.
It is clear that the same effect can be obtained even if the structure is arranged in the reverse order.

Furthermore, 5iOi may be formed as the gate insulating film using other methods, such as sputtering, or Si
Insulating substances other than O□ may be used.

Furthermore, although we have shown an example of using a Si thin film as a semiconductor, P
It is also possible to use a compound such as Ge, which can form a type and N type semiconductor through the deposition.

Furthermore, it is clear that the same effect can be obtained even if a material other than metal, such as a semiconductor or superconductor having a sufficiently high resistance, is used as the wiring.

An equivalent diagram of the CMOS inverter shown in FIG. 1 is shown in FIG. Drain electrode part 2 of NchTFT and PchTF
A feature is that a capacitance is added between the drain electrode portions 8 of the T. This capacitance has three effects. The first effect is that the CMOS inverter becomes more resistant to malfunction due to noise from the power supply. The second effect is that when the wiring between CMOS inverters extends over a long distance, the wiring resistance increases, which prevents the power supply voltage from dropping during switching. The third effect is that a capacitance exhibiting these effects can be realized with a small device occupation area.

[Effect of the invention 1] As described above, the present invention provides a low-pressure CVD method that is highly productive in mass production.
Since the semiconductor thin film into which dopants are introduced is formed using deposition methods such as atmospheric pressure CVD and plasma CVD, it is possible to form a CMO5 structure without using expensive and low-productivity ion implantation equipment. It has the characteristic that

Furthermore, the above-described manufacturing process for the CMO3 structure has a feature that it is possible to manufacture a stable high-performance semiconductor device over a large area due to the effect of the insulating film between the P-type semiconductor thin film and the N-type semiconductor thin film.

Another feature is that the capacitance between the power supply electrodes, which increases resistance to electrical noise, is created automatically and in a small area occupied by the device.

Furthermore, since there is no need for a high-temperature process necessary for activating dopants after ion implantation, an inexpensive glass substrate can be used as the insulating substrate.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams showing an inverter (inverting amplifier) as an example of a semiconductor device according to the present invention. (
FIG. 3(a) is a top view, and FIG. 3(b) is a cross-sectional view taken along AA' in FIG. FIGS. 2(a) to 2(e) are cross-sectional views showing one example of the manufacturing process of the semiconductor device according to the present invention shown in FIG. 1. FIG. 3 is a diagram showing an equinodal circuit of the semiconductor device according to the present invention shown in FIG. 1. 1...Insulating substrate 2...Nch TFT source electrode part 3...
Drain electrode part 4 of NchTFT...NchTF
T channel part 5... Gate insulating film 6 of Nch TFT... Gate electrode part 7... Gate insulating film 8 of Pch TFT...
Source electrode part 9 of PchTFT...PchTFT
Drain electrode part 10...Pch TFT channel part 11...Contact hole 12...Input signal wiring 13...Output signal wiring 14.15...More than power supply voltage supply wiring Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Tsumugi Mogami - (1 other person) 4+, ;+
”＼ , :', r ′, + knee (α) is 1 old

Claims (2)

[Claims] (1) Includes a structure in which an N-channel field-effect thin film transistor and a P-channel field-effect thin film transistor installed on an insulating substrate share a gate electrode and are configured such that at least a portion thereof overlaps. Characteristic semiconductor devices. (2) The method according to claim 1, wherein a deposition method such as a low pressure CVD method, an ordinary pressure CVD method, or a plasma CVD method is used as a film forming method for forming the N-type semiconductor thin film and the P-type semiconductor thin film. A method for manufacturing a semiconductor device.