JP2020126218A - Semiconductor substrate and display - Google Patents

Abstract

To provide a semiconductor substrate and a display that can perform driving by using a plurality of current paths.SOLUTION: A semiconductor substrate comprises: a first base material; a gate line G; a source line S; an insulating film; a first pixel electrode PE1, and a first transistor Tr1 and a second transistor Tr2 connected in parallel between the source line S and the first pixel electrode PE1. A first semiconductor layer SC1 of the first transistor Tr1 and a second semiconductor layer SC2 of the second transistor Tr2 each have a first area R1, a second area R2, and a channel area RC. The first semiconductor layer SC1 and the second semiconductor layer SC2 are in contact with a first surface that is a surface of the insulating film facing the source line S. The entirety of the respective channel areas RC of the first semiconductor layer SC1 and the second semiconductor layer SC2 are overlaid on the gate line G.SELECTED DRAWING: Figure 5

Description

Embodiments of the present invention relate to a semiconductor substrate and a display device.

As a display device, for example, an electrophoretic display device is known. In the electrophoretic display device, thin film transistors are used as switching elements. By increasing the channel width of the thin film transistor, the amount of current flowing through the thin film transistor can be increased.

JP 2012-60091 A JP, 2017-228560, A JP, 2010-217916, A JP 2006-349903 A

The present embodiment provides a semiconductor substrate and a display device that can be driven using a plurality of current paths.

The semiconductor substrate according to one embodiment,
A first base material, a gate line located above the first base material, a source line located above the first base material, a source line located above the gate line, and a position located below the source line An insulating film, a first pixel electrode located above the first base material, the gate line, and the source line, and an electrical connection between the source line and the first pixel electrode located above the first base material. A first transistor and a second transistor connected in parallel with one pixel electrode, wherein the first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor are respectively the source. A first region electrically connected to the line, a second region electrically connected to the first pixel electrode, and a channel region between the first region and the second region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface which is a surface of the insulating film on the source line side, and the first semiconductor layer and the second semiconductor layer have channel regions of the first semiconductor layer and the second semiconductor layer respectively. The whole is overlapped with the gate line.

Further, the display device according to one embodiment,
A first base material, a gate line located above the first base material, a source line located above the first base material, a source line located above the gate line, and a position located below the source line An insulating film, a first pixel electrode located above the first base material, the gate line, and the source line, and an electrical connection between the source line and the first pixel electrode located above the first base material. A semiconductor substrate including a first transistor and a second transistor connected in parallel with one pixel electrode, a second base material facing the first pixel electrode, the second base material, and the second base material. A counter substrate provided with a counter electrode positioned between the first pixel electrode and the first pixel electrode, and a counter substrate positioned between the first pixel electrode and the counter electrode; And a display function layer to which a voltage applied between the counter electrode and the counter electrode is applied, and the first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor are electrically connected to the source line, respectively. A first region electrically connected to the first pixel electrode, a second region electrically connected to the first pixel electrode, and a channel region between the first region and the second region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface of the insulating film, which is a surface on the source line side, and the entire channel regions of the first semiconductor layer and the second semiconductor layer are the whole. Overlaid on the gate line.

FIG. 1 is a plan view showing the configuration of the display device according to the first embodiment. FIG. 2 is a circuit diagram showing the display device. FIG. 3 is an equivalent circuit diagram showing the pixel shown in FIG. FIG. 4 is a sectional view showing a display panel of the display device. FIG. 5 is an enlarged plan view showing a part of the first substrate of the display device. 6 is a plan view showing a part of the first substrate of FIG. 5 in a further enlarged manner. The gate line, the first semiconductor layer, the second semiconductor layer, the source line, the first connection electrode, the second connection electrode, It is a figure which shows and an auxiliary gate electrode. FIG. 7 is a cross-sectional view showing the first substrate taken along the line VII-VII of FIG. FIG. 8 is a cross-sectional view showing the first substrate taken along line VIII-VIII of FIG. FIG. 9 is a table showing the determination results and the W/L values when the channel width and the channel length of each semiconductor layer shown in FIG. 6 are changed. FIG. 10 is an enlarged plan view showing a part of the first substrate of the display device according to the second embodiment. 11 is a cross-sectional view showing the first substrate taken along the line XI-XI of FIG. FIG. 12 is an enlarged plan view showing a part of the first substrate of the display device according to the third embodiment. FIG. 13 is a cross-sectional view showing the first substrate taken along the line XIII-XIII in FIG. FIG. 14 is a cross-sectional view showing the first substrate taken along the line XIV-XIV of FIG. FIG. 15 is a cross-sectional view showing the first substrate taken along the line XV-XV in FIG. 16 is a cross-sectional view showing the first substrate taken along the line XVI-XVI of FIG. FIG. 17 is an enlarged plan view showing a part of the first substrate of the display device according to the fourth embodiment. FIG. 18 is a cross-sectional view showing the first substrate taken along the line XVIII-XVIII in FIG. FIG. 19 is an enlarged plan view showing a part of the first substrate of the display device according to the fifth embodiment. 20 is a cross-sectional view showing the first substrate taken along the line XX-XX in FIG. 21 is a cross-sectional view showing the first substrate taken along line XXI-XXI of FIG. FIG. 22 is an enlarged plan view showing a part of the first substrate of the display device according to the sixth embodiment. 23 is a cross-sectional view showing the first substrate taken along the line XXIII-XXIII in FIG. FIG. 24 is an enlarged plan view showing a part of the first substrate of the display device according to the seventh embodiment. FIG. 25 is an enlarged plan view showing a part of the first substrate of the display device according to the eighth embodiment. FIG. 26 is an enlarged plan view showing a part of the first substrate of the display device according to the ninth embodiment. FIG. 27 is an enlarged plan view showing a part of the first substrate of the display device according to the tenth embodiment. FIG. 28 is an enlarged plan view showing a part of the first substrate of the display device according to the eleventh embodiment. FIG. 29 is an enlarged plan view showing a part of the first substrate of the display device according to the twelfth embodiment.

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and a person skilled in the art can easily think of appropriate modifications while keeping the gist of the invention, of course, is included in the scope of the invention. In addition, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part as compared with the actual mode, but this is merely an example, and the interpretation of the present invention will be understood. It is not limited. In the specification and the drawings, the same elements as those described above with reference to the already-explained drawings are designated by the same reference numerals, and detailed description thereof may be appropriately omitted.

(First embodiment)
First, the display device DSP according to the first embodiment will be described in detail. FIG. 1 is a plan view showing the configuration of the display device DSP according to the first embodiment.

As shown in FIG. 1, in the present embodiment, the first direction X and the second direction Y are orthogonal to each other. The direction referred to here is the direction indicated by the arrow in the figure, and the direction inverted by 180 degrees with respect to the arrow is the opposite direction. The first direction X and the second direction Y may intersect at an angle other than 90°. The third direction Z is orthogonal to the first direction X and the second direction Y, respectively. The third direction Z corresponds to the thickness direction of the display device DSP.

The display device DSP includes an active matrix type display panel PNL, a wiring board CB, an IC chip I1 and the like. The display panel PNL includes a first substrate SUB1 and a second substrate SUB2 arranged to face the first substrate SUB1. In the present embodiment, the first substrate SUB1 is formed in a rectangular shape, and the second substrate SUB2 is formed in a rectangular shape having a smaller outer shape than the first substrate SUB1.

In the following description, the direction from the first substrate SUB1 to the second substrate SUB2 is upward (or simply upward), and the direction from the second substrate SUB2 to the first substrate SUB1 is downward (or simply downward). When the “second member above the first member” and the “second member below the first member” are used, the second member may be in contact with the first member or may be located away from the first member. You may have. In the latter case, the third member may be interposed between the first member and the second member. Further, it is assumed that there is an observation position for observing the display device DSP on the tip side of the arrow indicating the third direction Z, and from this observation position, the direction toward the XY plane defined by the first direction X and the second direction Y is set. Seeing is called planar view.

The display panel PNL includes a display area DA for displaying an image and a non-display area NDA other than the display area DA. In the present embodiment, the non-display area NDA is formed in a frame shape.
Here, of the non-display area NDA, a strip-shaped area that is on the left side of the display area DA and extends in the second direction Y is a first area A1, and an area on the right side of the display area DA that is in the second direction Y. The extended strip-shaped region is the second region A2, the region below the display region DA is the strip-shaped region extending in the first direction X is the third region A3, and the region above the display region DA is the first region A3. The strip-shaped region extending in the direction X is referred to as a fourth region A4.

The display panel PNL includes gate drivers GD1 and GD2 and a source driver SD. The gate drivers GD1 and GD2 are configured to drive a gate line described later, the gate driver GD1 is arranged in the first area A1, and the gate driver GD2 is arranged in the second area A2. The source driver SD is configured to drive a source line, which will be described later, and is arranged in the third area A3. The pad group is an outer lead bonding pad group and is arranged in the third region A3. The pads included in the pad group are electrically connected to the gate drivers GD1 and GD2, the source driver SD, and the like.

The wiring board CB is physically connected to the third area A3 of the first substrate SUB1 and electrically connected to the plurality of pads of the pad group PG. The IC chip I1 is mounted on the wiring board CB. However, unlike the present embodiment, the IC chip I1 may be mounted in a region of the third region A3 of the first substrate SUB1 that does not face the second substrate SUB2. The IC chip I1 can give a signal to the gate drivers GD1 and GD2, the source driver SD, and the like via the wiring board CB and the like.

FIG. 2 is a circuit diagram showing the display device DSP. FIG. 3 is an equivalent circuit diagram showing the pixel PX shown in FIG. Note that, in FIG. 2, not all pixels PX and all wirings are shown.
As shown in FIGS. 2 and 3, the display panel PNL includes a first base material 1, a plurality of pixels PX arranged in a matrix above the first base material 1 in the display area DA, and a plurality of gates. The line G, a plurality of source lines S, and a plurality of capacitance lines CW are provided.

The gate line G is connected to the gate driver GD, extends in the first direction X, and is electrically connected to the plurality of pixels PX arranged in the first direction X. The source line S is connected to the source driver SD, extends in the second direction Y, and is electrically connected to the plurality of pixels PX arranged in the second direction Y. The capacitance wiring CW extends in the first direction X or the second direction Y. In the present embodiment, the capacitor wiring CW extends in the second direction Y and is electrically connected to the plurality of pixels PX arranged in the second direction Y. The plurality of capacitance lines CW are bundled in the non-display area NDA and connected to the IC chip I1.

The gate driver GD is configured to supply the control signal SG to the gate line G and drive the gate line G. The source driver SD is configured to supply an image signal (for example, a video signal) Vsig to the source line S and drive the source line S. The IC chip I1 applies a constant voltage Vpc to the capacitance wiring CW, and the capacitance wiring CW is fixed at a constant potential. Further, the IC chip I1 applies a common voltage Vcom to the counter electrode CE, and the counter electrode CE is fixed at a constant potential (common potential). In the present embodiment, the counter electrode CE can be referred to as a common electrode because it is shared by all the pixels PX. In the present embodiment, the capacitance wiring CW is set to the same potential as the counter electrode CE, but it may be set to a potential different from that of the counter electrode CE. The gate driver GD, the source driver SD, and the IC chip I1 form a driving unit for driving the plurality of pixels PX.

Each pixel PX includes a first transistor Tr1, a second transistor Tr2, a first capacitor C1 and a second capacitor C2. The first transistor Tr1 and the second transistor Tr2 are configured of the same conductivity type, for example, a P-channel type thin film transistor (TFT). Each semiconductor layer of the first transistor Tr1 and the second transistor Tr2 is formed of an oxide semiconductor. Note that the semiconductor layer may use a semiconductor other than an oxide semiconductor, such as polycrystalline silicon such as low temperature polycrystalline silicon or amorphous silicon. Each of the first transistor Tr1 and the second transistor Tr2 may be composed of an N-channel type TFT. In addition, the following description will be made on a transistor Tr including an oxide semiconductor.

The first transistor Tr1 and the second transistor Tr2 have a first terminal t1, a second terminal t2, and a control terminal t3, respectively. In this embodiment, the control terminal t3 functions as a gate electrode, one of the first terminal t1 and the second terminal t2 functions as a source electrode, and the other of the first terminal t1 and the second terminal t2 functions as a drain electrode. ing. The first transistor Tr1 and the second transistor Tr2 are electrically connected in parallel between the source line S and the pixel electrode PE.

In each of the first transistor Tr1 and the second transistor Tr2, the first terminal t1 is connected to the source line S, the second terminal t2 is connected to the pixel electrode PE, and the control terminal t3 is connected to the gate line G. As a result, each of the first transistor Tr1 and the second transistor Tr2 is switched to the conductive state or the non-conductive state by the control signal SG applied to the gate line G. The image signal Vsig is given to the pixel electrode PE via the source line S and the transistors Tr1 and Tr2 in the conductive state.

The first capacitance C1 and the second capacitance C2 are capacitors. The first capacitance C1 is connected between the pixel electrode PE and the capacitance wiring CW. The second capacitor C2 is connected between the pixel electrode PE and the counter electrode CE.

FIG. 4 is a sectional view showing the display panel PNL. Here, attention is paid to one pixel PX.
As shown in FIG. 4, the first substrate SUB1 includes a first base material 1, a base layer 10 provided on the first base material 1, a pixel electrode PE provided on the base layer 10, Equipped with. The second substrate SUB2 includes a second base material 2 facing the pixel electrode PE, and a counter electrode CE located between the second base material 2 and the pixel electrode PE and facing the pixel electrode PE. The counter electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In this embodiment, the first substrate SUB1 is a semiconductor substrate and the second substrate SUB2 is a counter substrate. The first base material and the second base material 2 are formed of an insulating material such as resin or glass. In the present embodiment, the second base material 2 is located on the screen side (observation side) and is light transmissive. Since the first base material is located on the opposite side of the screen, it may be opaque or transparent.

The display function layer DL of the display panel PNL is located between the pixel electrode PE and the counter electrode CE. A voltage applied between the pixel electrode PE and the counter electrode CE is applied to the display function layer DL. In this embodiment, the display device DSP is an electrophoretic display device, and the display function layer DL is an electrophoretic layer. The display function layer DL is formed by a plurality of microcapsules 30 arranged with almost no space in the XY plane.
The adhesive layer AL of the display panel PNL is located between the pixel electrode PE and the display function layer DL.

The microcapsule 30 is, for example, a spherical body having a particle size of about 20 μm to 70 μm. In the illustrated example, many microcapsules 30 are arranged between one pixel electrode PE and the counter electrode CE due to scale, but one side has a rectangular shape with a length of about 100 to several hundreds μm. About one to ten microcapsules 30 are arranged in the pixel PX having a shape or a polygonal shape.

The microcapsule 30 includes a dispersion medium 31, a plurality of black particles 32, and a plurality of white particles 33. The black particles 32 and the white particles 33 may be referred to as electrophoretic particles. The outer shell portion (wall film) 34 of the microcapsule 30 is formed using, for example, a transparent resin such as acrylic resin. The dispersion medium 31 is a liquid that disperses the black particles 32 and the white particles 33 in the microcapsules 30. The black particles 32 are particles (polymer or colloid) made of a black pigment such as aniline black, and are positively charged, for example. The white particles 33 are particles (polymer or colloid) made of white pigment such as titanium dioxide, and are negatively charged, for example. Various additives can be added to these pigments if necessary. Instead of the black particles 32 and the white particles 33, pigments such as red, green, blue, yellow, cyan and magenta may be used.

In the display function layer DL having the above configuration, when the pixel PX is displayed in black, the pixel electrode PE is held at a relatively higher potential than the counter electrode CE. That is, when the potential of the counter electrode CE is used as the reference potential, the pixel electrode PE is held in the positive polarity. As a result, the positively charged black particles 32 are attracted to the counter electrode CE, while the negatively charged white particles 33 are attracted to the pixel electrode PE. As a result, black is visually recognized when observing the pixel PX from the counter electrode CE side. On the other hand, when displaying the pixel PX in white, the pixel electrode PE is held in the negative polarity when the potential of the counter electrode CE is used as the reference potential. As a result, the negatively charged white particles 33 are attracted to the counter electrode CE side, while the positively charged black particles 32 are attracted to the pixel electrode PE. As a result, when this pixel PX is observed, white is visually recognized.

In the present embodiment, the pixel electrode PE is in contact with the adhesive layer AL. However, an insulating protective layer may be interposed between the pixel electrode PE and the adhesive layer AL, and the pixel electrode PE may be protected by the protective layer.

FIG. 5 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP.
As shown in FIG. 5, the gate line G extends in the first direction X. The source line S extends in the second direction Y and intersects the gate line G. The pixel electrode PE has a first pixel electrode PE1 and a second pixel electrode PE2 that are electrically connected to each other. The gate line G and the source line S intersect with the first pixel electrode PE1. The second pixel electrode PE2 is located at a distance from the gate line G in the second direction Y.

The first semiconductor layer SC1 of the first transistor Tr1 and the second semiconductor layer SC2 of the second transistor Tr2 are electrically connected to the first region R1 electrically connected to the source line S and the pixel electrode PE, respectively. It also has a second region R2 and a channel region RC between the first region R1 and the second region R2. The entire channel regions RC of the first semiconductor layer SC1 and the second semiconductor layer SC2 are overlaid on the same gate line G. In the present embodiment, the entire first semiconductor layer SC1 and the entire second semiconductor layer SC2 are overlaid on the same gate line G.

The first connection electrode EL1 is overlapped with the gate line G and is located at a distance from the source line S in the first direction X.
The second connection electrode EL2 extends in the second direction Y. One end of the second connection electrode EL2 is located between the source line S and the first connection electrode EL1 in the region overlapping the gate line G, and overlaps the second region R2 of each semiconductor layer SC. The other end of the second connection electrode EL2 overlaps the second pixel electrode PE2.

The capacitor electrode OE is located at a distance from the semiconductor layer SC, the source line S, the first connection electrode EL1, and the second connection electrode EL2, and overlaps the first pixel electrode PE1 and the second pixel electrode PE2, respectively. In the present embodiment, the entire capacitance electrode OE is located inside the first pixel electrode PE1 and inside the second pixel electrode PE2 in plan view.
The connection wiring NW extends in the second direction Y, intersects the gate line G, and does not intersect the source line S. The connection wiring NW connects two adjacent capacitance electrodes OE in the second direction Y with the gate line G interposed therebetween. In the present embodiment, the plurality of connection wirings NW and the plurality of capacitance electrodes OE arranged in the second direction Y are integrally formed to form the capacitance wiring CW.

The auxiliary gate electrode AE overlaps each semiconductor layer SC and the first connection electrode EL1. It is sufficient that the auxiliary gate electrode AE at least overlaps the entire channel regions RC of both the first semiconductor layer SC1 and the second semiconductor layer SC2 in a plan view. In the present embodiment, the auxiliary gate electrode AE overlaps the entire first semiconductor layer SC1 and the entire second semiconductor layer SC2.
The third connection electrode EL3 is located at a distance from the auxiliary gate electrode AE and overlaps the second connection electrode EL2 and the first pixel electrode PE1.

The gate line G and the second pixel electrode PE2 are formed of the same material. The source line S, the first connection electrode EL1, the second connection electrode EL2, the capacitance electrode OE, and the connection wiring NW are formed of the same material. The auxiliary gate electrode AE and the third connection electrode EL3 are formed of the same material. The gate line G, the second pixel electrode PE2, the source line S, the first connection electrode EL1, the second connection electrode EL2, the capacitance electrode OE, the connection wiring NW, the auxiliary gate electrode AE, and the third connection electrode EL3 are made of Al (aluminum). ), Ti (titanium), Ag (silver), Mo (molybdenum), W (tungsten), Cu (copper), Cr (chromium), and the like, alloys formed by combining these metal materials, It may have a single-layer structure or a multi-layer structure.

FIG. 6 is a plan view showing a part of the first substrate SUB1 of FIG. 5 in a further enlarged manner. The gate line G, the first semiconductor layer SC1, the second semiconductor layer SC2, the source line S, and the first connection electrode EL1. FIG. 6 is a diagram showing a second connection electrode EL2 and an auxiliary gate electrode AE.
As shown in FIG. 6, the first semiconductor layer SC1 and the second semiconductor layer SC2 have a major axis AX1 in the first direction X in which the gate line G extends and a minor axis AX2 in the second direction Y. .. In the present embodiment, the first semiconductor layer SC1 and the second semiconductor layer SC2 are arranged in the width direction of the gate line G (second direction Y). The width WI of the gate line G is larger than the sum of the length of the short axis AX2 of the first semiconductor layer SC1 and the length of the short axis AX2 of the second semiconductor layer SC2.
As an example, the short axis AX2 (channel width W) of each of the first semiconductor layer SC1 and the second semiconductor layer SC2 is 1.5 μm, the width WI of the gate line G is 11 μm, and the gate line G is substantially the same. The width WI is set to be larger than twice the sum of the length of the short axis AX2 of the first semiconductor layer SC1 and the length of the short axis of the second semiconductor layer SC2. When the manufacturing position shift occurs by making the width WI of the gate line G larger than the sum of the length of the short axis AX2 of the first semiconductor layer SC1 and the length of the short axis AX2 of the second semiconductor layer SC2. Also in the above, the entire first semiconductor layer SC1 and the second semiconductor layer SC2 can be accommodated within the width WI of the gate line G.
Further, in the structure shown in FIG. 6, the second connection electrode EL2 has the extended end portion EX that extends over the first semiconductor layer SC1 and extends in the second direction Y on the side opposite to the second semiconductor layer SC2. There is. For example, when the extended end portion EX of the second connection electrode EL2 is located inside the first semiconductor layer SC1 due to a manufacturing misalignment, the originally required characteristics of the first transistor Tr1 may not be reached, or It is assumed that the characteristics of the first transistor Tr1 and the second transistor Tr2 may be different from each other. Since the extended end portion EX of the second connection electrode EL2 has a structure that extends beyond the first semiconductor layer SC1, it is possible to prevent a change in the characteristics of the transistor due to a positional shift.

The channel length and the channel width in the channel regions RC of the first semiconductor layer SC1 and the second semiconductor layer SC2 are L and W, respectively. In the present embodiment, it is desirable that W/L≦0.75. The relationship between the channel length (L) and the channel width (W) will be described later.

Next, the sectional structure of the display panel PNL will be described. FIG. 7 is a cross-sectional view of the first substrate SUB1 taken along the line VII-VII of FIG. FIG. 8 is a cross-sectional view showing the first substrate SUB1 taken along the line VIII-VIII of FIG.
As shown in FIG. 7, the insulating layer 11 is formed on the first base material 1. The gate line G is formed on the insulating layer 11. The insulating layer 12 is formed on the insulating layer 11 and the gate line G.

The semiconductor layer SC such as the first semiconductor layer SC1 is provided on the insulating layer 12. The insulating layer 12 has a first surface 12s which is a surface on the source line S side. The semiconductor layer SC such as the first semiconductor layer SC1 is in contact with the first surface 12s. The source line S, the first connection electrode EL1, the second connection electrode EL2, and the connection wiring NW are provided on the insulating layer 12 on which the semiconductor layer SC is formed. The source line S is located on the first region R1 of the semiconductor layer SC such as the first semiconductor layer SC1, is in contact with the first region R1, and is electrically connected to the first region R1. The second connection electrode EL2 is located on the second region R2 of the semiconductor layer SC such as the first semiconductor layer SC1, is in contact with the second region R2, and is electrically connected to the second region R2. The first connection electrode EL1 is electrically connected to the gate line G. Here, the first connection electrode EL1 is in contact with the gate line G through the contact hole CH1 formed in the insulating layer 12.

The insulating layer 13 is formed on the insulating layer 12, on which the insulating layer 12, the semiconductor layer SC, the source line S, the first connection electrode EL1, the second connection electrode EL2, and the connection wiring NW are formed. The auxiliary gate electrode AE is provided on the insulating layer 13 and contacts the first connection electrode EL1 through a contact hole CH2 formed in the insulating layer 13. The auxiliary gate electrode AE is electrically connected to the gate line G via the first connection electrode EL1.

The auxiliary gate electrode AE faces at least the channel region RC of the semiconductor layer SC. The auxiliary gate electrode AE sandwiches the first semiconductor layer SC1 and the second semiconductor layer SC2 together with the gate line G. For example, in the first transistor Tr1, the gate line G and the auxiliary gate electrode AE each function as a gate electrode. The first transistor Tr1 is a thin film transistor having a dual gate structure. A part of the gate line G, the first semiconductor layer SC1, the auxiliary gate electrode AE, and the like form the first transistor Tr1. The second transistor Tr2 has a sectional structure similar to that of the first transistor Tr1. The gate line G, the source line S, and the auxiliary gate electrode AE are located above the first base material 1. The first transistor Tr1 and the second transistor Tr2 are also located above the first base material 1.

The insulating layer 14 is formed on the insulating layer 13 and the auxiliary gate electrode AE. The insulating layer 11, the insulating layer 12, and the insulating layer 13 are all inorganic insulating layers formed of an inorganic insulating material such as silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). Is equivalent to. Each of the insulating layer 11, the insulating layer 12, and the insulating layer 13 may have a single-layer structure or a laminated structure. The insulating layer 14 corresponds to an organic insulating layer formed of an organic insulating material such as acrylic resin. Above the first base material 1, the above-described base layer 10 is formed from the insulating film 11 to the insulating layer 14.

The first pixel electrode PE1 is located above the first base material 1, the gate line G, and the source line S. In the present embodiment, the first pixel electrode PE1 is provided on the insulating layer 14. The first pixel electrode PE1 is composed of a laminated body of a light reflection layer FL and a transparent conductive layer TL. The light reflection layer FL is provided on the insulating layer 14. The light reflection layer FL is formed of a metal material such as Al, Ti, Ag, Mo, W, Cu, Cr, or an alloy combining these metal materials, and may have a single-layer structure or a multi-layer structure. May be The light reflection layer FL of this embodiment is a light reflection conductive layer.

The transparent conductive layer TL is provided on the insulating layer 14 and the light reflection layer FL, and is in contact with the light reflection layer FL. In the present embodiment, the size of the transparent conductive layer TL is larger than the size of the light reflecting layer FL, and the transparent conductive layer TL completely covers the upper surface and the side surface of the light reflecting layer FL. The transparent conductive layer TL is in contact with the insulating layer 14 outside the light reflection layer FL. However, the sizes of the light reflection layer FL and the transparent conductive layer TL are not limited to those in the present embodiment, and various modifications are possible. For example, the size of the transparent conductive layer TL is the same as the size of the light reflection layer FL, and the transparent conductive layer TL may be formed so as to completely overlap the light reflection layer FL. In the present embodiment, the second capacitance C2 corresponds to the capacitance formed between the first pixel electrode PE1 and the counter electrode CE.

As shown in FIG. 8, the second pixel electrode PE2 is located between the first base material 1 and the first pixel electrode PE1. In the present embodiment, the second pixel electrode PE2 is provided on the insulating layer 11 and covered with the insulating layer 12. The second connection electrode EL2 is provided on the insulating layer 12 and covered with the insulating layer 13. The second connection electrode EL2 is in contact with the second pixel electrode PE2 through the contact hole CH3 formed in the insulating layer 12.

The capacitance electrode OE is located between the first pixel electrode PE1 and the second pixel electrode PE2. In the present embodiment, the capacitive electrode OE is provided on the insulating layer 12 and covered with the insulating layer 13. The capacitance electrode OE is capacitively coupled to each of the first pixel electrode PE1 and the second pixel electrode PE2. The sum of the capacitance formed between the first pixel electrode PE1 and the capacitance electrode OE and the capacitance formed between the second pixel electrode PE2 and the capacitance electrode OE is the first capacitance C1. Is equivalent to.

The third connection electrode EL3 is provided on the insulating layer 13 and covered with the insulating layer 14. The third connection electrode EL3 is in contact with the second connection electrode EL2 through the contact hole CH4 formed in the insulating layer 13.

The light reflection layer FL has an opening surrounding the contact hole CH5 formed in the insulating layer 14. The transparent conductive layer TL is in contact with the third connection electrode EL3 through the opening of the light reflection layer FL and the contact hole CH5. From the above, the second pixel electrode PE2 is electrically connected to the first pixel electrode PE1 via the second connection electrode EL2 and the third connection electrode EL3.

As shown in FIGS. 5, 7, and 8, the gate line G and the second pixel electrode PE2 are formed of the same material and located in the same layer. The source line S, the plurality of capacitance electrodes OE, the plurality of connection wirings NW, the first connection electrode EL1, and the second connection electrode EL2 are formed of the same material and are located in the same layer. The auxiliary gate electrode AE and the third connection electrode EL3 are formed of the same material and located in the same layer.

Next, the relationship between the channel length (L) and the channel width (W) of each semiconductor layer SC will be described. FIG. 9 is a table showing the determination results and the W/L values when the channel width (W) and the channel length (L) of each semiconductor layer SC shown in FIG. 6 are changed. In the figure, the value of W/L is enclosed in parentheses.

As shown in FIG. 9, as a result of judging various transistors Tr under the same condition, A or B is described. The determination was performed, for example, by applying the same current to various transistors Tr. When the transistor Tr functions as a switch without breaking the transistor Tr, it is determined as A. On the other hand, when the transistor Tr was destroyed and the transistor Tr did not function as a switch, it was determined to be B. It is assumed that an excessive current flows in the transistor Tr and the transistor Tr is destroyed due to heat generation deterioration.
For example, Patent Document 3 and Patent Document 4 described in the above-mentioned prior art documents are electrophoretic devices, and it is described that a high voltage of 30 V or higher is required for moving particles in microcapsules. Under the conditions shown in FIG. 9, a high-voltage current of, for example, 30 V or more is applied to the gate and the source of one transistor Tr including an oxide semiconductor for evaluation.
When the value of W/L was 0.75 or less, all the results were A judgments. Therefore, it is desirable to set the W/L value to 0.75 or less.

According to the display device DSP according to the first embodiment configured as described above, the first substrate SUB1 includes the first base material 1, the gate line G, the source line S, and the first pixel electrode PE1. , And a first transistor Tr1 and a second transistor Tr2 connected in parallel between the source line S and the first pixel electrode PE1. Therefore, as compared with the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel can be substantially doubled in current while maintaining the allowable current that can flow in one transistor Tr. The electrode PE can be driven.

The semiconductor layers SC of the first transistor Tr1 and the second transistor Tr2 each have a first region R1, a second region R2, and a channel region RC. The first region R1 is electrically connected to the source line S. The second region R2 is electrically connected to the first pixel electrode PE1. The channel region RC is located between the first region R1 and the second region R2. Each semiconductor layer SC has a major axis AX1 in the direction in which the gate line G extends, and is entirely overlaid on the gate line G. Therefore, for example, when it is necessary to increase the width of the gate line G in order to apply the high-voltage control signal SG to the gate line G, each semiconductor layer SC can be entirely overlapped with the gate line G.
From the above, it is possible to obtain a semiconductor substrate and a display device that can be driven using a plurality of current paths. In the first embodiment, the first substrate SUB1 and the display device DSP capable of driving the pixel electrode PE can be obtained by using the first semiconductor layer SC1 and the second semiconductor layer SC2.

(Second embodiment)
Next, the display device DSP according to the second embodiment will be described. FIG. 10 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the second embodiment.
As shown in FIG. 10, the display device DSP of the second embodiment is different from the first embodiment in that the capacitance wiring CW extends in the first direction X. In the present embodiment, the plurality of connection wirings NW and the plurality of capacitance electrodes OE arranged in the first direction X are electrically connected to each other to form the capacitance wiring CW. The connection wiring NW does not intersect with the gate line G but does intersect with the source line S.

Each connection wiring NW is composed of a connection electrode NW1, a connection electrode NW2, and a cross electrode NW3. The connection electrode NW1 is electrically connected to the one capacitance electrode OE and is located at a distance from the source line S. The connection electrode NW2 is electrically connected to the other capacitance electrode OE and is located at a distance from the source line S. In the present embodiment, the connection electrode NW1 is formed integrally with one capacitance electrode OE, and the connection electrode NW2 is formed integrally with the other capacitance electrode OE.

The crossing electrode NW3 intersects the source line S and is overlapped with the connection electrode NW1 and the connection electrode NW2, respectively. The width (length in the second direction Y) of the cross electrode NW3 is smaller in the region intersecting with the source line S than in the region overlapping with the connection electrodes NW1 and NW2. Therefore, the load on the source line S can be reduced compared to the case where the width of the cross electrode NW3 is not narrowed in the region intersecting with the source line S.

11 is a cross-sectional view showing the first substrate SUB1 taken along the line XI-XI of FIG.
As shown in FIG. 11, the cross electrode NW3 is provided on the insulating layer 11. The cross electrode NW3 is formed of the same material as the second pixel electrode PE2 in the same layer. The connection electrode NW1 and the connection electrode NW2 are provided on the insulating layer 12. The connection electrode NW1 and the connection electrode NW2 are formed of the same material in the same layer as the capacitance electrode OE, the source line S, and the like. The connection electrode NW1 passes through a contact hole CH6 formed in the insulating layer 12 and is in contact with the cross electrode NW3. The connection electrode NW2 passes through the contact hole CH7 formed in the insulating layer 12 and is in contact with the cross electrode NW3.

Also in the display device DSP according to the second embodiment configured as described above, the same effect as in the first embodiment can be obtained. The capacitance wiring CW does not intersect with the gate line G. Therefore, the load on the gate line G can be reduced as compared with the case where the capacitance line CW intersects with the gate line G. As a result, the driving capability of the gate line G can be further increased.

(Third Embodiment)
Next, the display device DSP according to the third embodiment will be described. FIG. 12 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the third embodiment.
As shown in FIG. 12, in the display device DSP of the third embodiment, the source line S extends vertically across the center of the pixel PX, and the capacitor wiring CW extends in the first direction X. The point, the first semiconductor layer SC1 and the second semiconductor layer SC2 are aligned and integrally formed in the first direction X, and the second pixel electrode PE2 and the capacitor electrode OE are divided in the first direction X, respectively. This is different from the first embodiment. For example, the connection wiring NW is formed of the same material as the capacitance electrode OE and is located in the same layer as the capacitance electrode OE. A region overlapping the first pixel electrode PE1 is classified into a first domain DOa and a second domain DOb which are adjacent to each other in the first direction X.

The second pixel electrode PE2 has a first segment SEa and a second segment SEb. The first segment SEa is located in the first domain DOa and spaced apart from the gate line G. The second segment SEb is located in the second domain DOb and is spaced from the gate line G and the first segment SEa.

The first semiconductor layer SC1 and the second semiconductor layer SC2 are arranged in the first direction X. The second region R2 and the channel region RC of the first semiconductor layer SC1 are located in the first domain DOa. The second region R2 and the channel region RC of the second semiconductor layer SC2 are located in the second domain DOb. The first region R1 of the first semiconductor layer SC1 and the first region R1 of the second semiconductor layer SC2 are integrally formed and overlap the source line S. In the present embodiment, the first semiconductor layer SC1 and the second semiconductor layer SC2 that are integrally formed are entirely overlaid on the same gate line G.

The source line S intersects the gate line G and is located on the boundary line BL between the first domain DOa and the second domain DOb.
The first connection electrode EL1 is located in the first domain DOa or the second domain DOb, overlaps with the gate line G, and is located at a distance from the source line S in the first direction X. In the present embodiment, the first connection electrode EL1 is located in the second domain DOb.

The second connection electrode EL2a is located in the first domain DOa, extends in the second direction Y, and is located at a distance from the source line S. One end of the second connection electrode EL2a overlaps the second region R2 of the first semiconductor layer SC1 in the region overlapping the gate line G. The other end of the second connection electrode EL2a overlaps with the first segment SEa and is electrically connected to the first segment SEa.

The second connection electrode EL2b is located in the second domain DOb, extends in the second direction Y, and is located at a distance from the source line S. One end of the second connection electrode EL2b is located between the source line S and the first connection electrode EL1 in a region overlapping the gate line G, and overlaps the second region R2 of the second semiconductor layer SC2. The other end of the second connection electrode EL2b overlaps the second segment SEb and is electrically connected to the second segment SEb.

The capacitance electrode OE has a first capacitance electrode OEa, a second capacitance electrode OEb, and a cross electrode OEc. The cross electrode OEc intersects with the source line S and is located at a distance from each of the first segment SEa and the second segment SEb.
The first capacitance electrode OEa is located in the first domain DOa, is overlapped with the first segment SEa, the cross electrode OEc, and the first pixel electrode PE1, and is spaced apart from the second connection electrode EL2a and the source line S, respectively. It is set aside.
The second capacitance electrode OEb is located in the second domain DOb, overlaps with the second segment SEb, the crossing electrode OEc, and the first pixel electrode PE1, respectively, and has the first connection electrode EL1, the second connection electrode EL2b, and the source. Spaced on each of the lines S.

In the description of FIG. 12, of the three pixels PX arranged in the first direction X, the capacitance electrode OE of the central pixel PX will be simply referred to as the capacitance electrode OE, and the capacitance electrode OE of the pixel PX at the left end will be referred to as another capacitance. It is referred to as an electrode OE, and the capacitance electrode OE of the pixel PX at the right end is referred to as a third capacitance electrode OE. The other capacitance electrode OE is adjacent to the first capacitance electrode OEa of the capacitance electrode OE. The third capacitance electrode OE is adjacent to the second capacitance electrode OEb, and is positioned to sandwich the capacitance electrode OE together with other capacitance electrodes OE.

Each of the connection wiring NWa and the other connection wiring NWb extends in the first direction X, does not intersect with the gate line G, and does not intersect with the source line S. The connection wiring NWa connects the first capacitance electrode OEa of the capacitance electrode OE and another capacitance electrode OE. The connection wiring NWb connects the second capacitance electrode OEb of the capacitance electrode OE and the third capacitance electrode OE.
In the present embodiment, the plurality of connection wirings NW and the plurality of capacitance electrodes OE arranged in the first direction X are connected to each other to form the capacitance wiring CW.

The auxiliary gate electrode AE overlaps each semiconductor layer SC and the first connection electrode EL1. It is sufficient that the auxiliary gate electrode AE at least overlaps the entire channel regions RC of both the first semiconductor layer SC1 and the second semiconductor layer SC2 in a plan view. In the present embodiment, the auxiliary gate electrode AE overlaps the entire first semiconductor layer SC1 and the entire second semiconductor layer SC2. Further, in the present embodiment, the auxiliary gate electrode AE intersects with the source line S.
The third connection electrode EL3 is located at a distance from the auxiliary gate electrode AE, and overlaps the second connection electrode EL2a, the second connection electrode EL2b, and the first pixel electrode PE1.

When the boundary line BL is the axis of symmetry, a group of the first segment SEa, the second connection electrode EL2a, and the first capacitance electrode OEa, and a group of the second segment SEb, the second connection electrode EL2b, and the second capacitance electrode OEb And are arranged substantially in line symmetry.

Next, the sectional structure of the display panel PNL will be described. FIG. 13 is a cross-sectional view showing the first substrate SUB1 taken along the line XIII-XIII of FIG. FIG. 14 is a cross-sectional view of the first substrate SUB1 taken along the line XIV-XIV of FIG. FIG. 15 is a cross-sectional view showing the first substrate SUB1 taken along the line XV-XV in FIG.

As shown in FIG. 13, the first semiconductor layer SC1 and the second semiconductor layer SC2 are provided on the insulating layer 12 and are integrally formed. The source line S is located on the common first region R1 of the first semiconductor layer SC1 and the second semiconductor layer SC2, is in contact with the first region R1, and is electrically connected to the first region R1. The second connection electrode EL2a is located on the second region R2 of the first semiconductor layer SC1, is in contact with the second region R2, and is electrically connected to the second region R2. The second connection electrode EL2b is located on the second region R2 of the second semiconductor layer SC2, is in contact with the second region R2, and is electrically connected to the second region R2. The insulating layer 13 covers the insulating layer 12, the source line S, the first connection electrode EL1, the second connection electrode EL2a, and the second connection electrode EL2b.

As shown in FIG. 14, the first segment SEa and the second segment SEb are provided on the insulating layer 11 and covered with the insulating layer 12. The source line S, the second connection electrode EL2a, and the second connection electrode EL2b are provided on the insulating layer 12 and covered with the insulating layer 13.
Here, as shown in FIG. 16, the second connection electrode EL2a faces the first segment SEa and is in contact with the first segment SEa through the contact hole CH3a formed in the insulating layer 12. The second connection electrode EL2b faces the second segment SEb and is in contact with the second segment SEb through a contact hole CH3b formed in the insulating layer 12.

As shown in FIG. 14, the third connection electrode EL3 is provided on the insulating layer 13 and covered with the insulating layer 14. The third connection electrode EL3 is in contact with the second connection electrode EL2a through the contact hole CH4a formed in the insulating layer 13, and is in contact with the second connection electrode EL2b through the contact hole CH4b formed in the insulating layer 13. .. The first pixel electrode PE1 is in contact with the third connection electrode EL3 through the contact hole CH5. From the above, the first segment SEa is electrically connected to the first pixel electrode PE1 via the second connection electrode EL2a and the third connection electrode EL3. The second segment SEb is electrically connected to the first pixel electrode PE1 via the second connection electrode EL2b and the third connection electrode EL3.

As shown in FIG. 15, the first segment SEa, the second segment SEb, and the cross electrode OEc are provided on the insulating layer 11 and covered with the insulating layer 12. In addition to the source line S, the first capacitance electrode OEa and the second capacitance electrode OEb are provided on the insulating layer 12. The first capacitance electrode OEa faces the first segment SEa and the cross electrode OEc, and contacts the cross electrode OEc through a contact hole CH8 formed in the insulating layer 12. The second capacitance electrode OEb faces the second segment SEb and the cross electrode OEc, and contacts the cross electrode OEc through a contact hole CH9 formed in the insulating layer 12. From the above, the crossing electrode OEc electrically connects the first capacitance electrode OEa and the second capacitance electrode OEb.

The source line S, the first capacitance electrode OEa, and the second capacitance electrode OEb are covered with the insulating layer 13. The insulating layer 14 and the first pixel electrode PE1 are sequentially provided on the insulating layer 13. In the first domain DOa, the first capacitance electrode OEa is located between the first segment SEa and the first pixel electrode PE1. In the second domain DOb, the second capacitance electrode OEb is located between the second segment SEb and the first pixel electrode PE1.

The first capacitance electrode OEa is capacitively coupled to each of the first segment SEa and the first pixel electrode PE1. The second capacitance electrode OEb is capacitively coupled to each of the second segment SEb and the first pixel electrode PE1. The capacitance formed between the first pixel electrode PE1 and the first capacitance electrode OEa, the capacitance formed between the first segment SEa and the first capacitance electrode OEa, and the first pixel electrode PE1. The sum of the capacitance formed between the second capacitance electrode OEb and the second capacitance electrode OEb and the capacitance formed between the first segment SEa and the second capacitance electrode OEb corresponds to the first capacitance C1. doing.

As shown in FIGS. 12 to 16, the gate line G, the first segment SEa, the second segment SEb, and the cross electrode OEc are formed of the same material and located in the same layer. The source line S, the first capacitance electrode OEa, the second capacitance electrode OEb, the connection wiring NW, the first connection electrode EL1, the second connection electrode EL2a, and the second connection electrode EL2b are formed of the same material and located in the same layer. doing. The auxiliary gate electrode AE and the third connection electrode EL3 are formed of the same material and located in the same layer.

Also in the display device DSP according to the third embodiment configured as described above, the same effect as in the second embodiment can be obtained. The capacitance electrode OE is divided into a first capacitance electrode OEa and a second capacitance electrode OEb, and the second pixel electrode PE2 is divided into a first segment SEa and a second segment SEb. Compared with the second embodiment, the area of the electrodes of the respective capacitors that form the first capacitor C1 can be reduced, so that destruction of the capacitors due to ESD (electro-static discharge) can be less likely to occur. it can.

(Fourth Embodiment)
Next, the display device DSP according to the fourth embodiment will be described. FIG. 17 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the present fourth embodiment.

As shown in FIG. 17, the configuration of the connection wiring NW differs from that of the first embodiment. In the present embodiment, each connection wiring NW includes a connection electrode NW5, a connection electrode NW6, and a cross electrode NW7. The connection electrode NW5 is electrically connected to the one capacitance electrode OE and is located at a distance from the gate line G. The connection electrode NW6 is electrically connected to the other capacitance electrode OE and is located at a distance from the gate line G. In the present embodiment, the connection electrode NW5 is formed integrally with one capacitance electrode OE, and the connection electrode NW6 is formed integrally with the other capacitance electrode OE. The cross electrode NW7 intersects the gate line G and is overlapped with the connection electrode NW5 and the connection electrode NW6, respectively.

FIG. 18 is a cross-sectional view showing the first substrate SUB1 taken along the line XVIII-XVIII of FIG.
As shown in FIG. 18, the cross electrode NW7 is located in a layer different from the layer in which the gate line G and the source line S are located. The cross electrode NW7 is provided on the insulating layer 13. The crossing electrode NW7 is formed of the same material and in the same layer as the auxiliary gate electrode AE and the third connection electrode EL3. The connection electrode NW5 and the connection electrode NW6 are provided on the insulating layer 12. The connection electrode NW5 and the connection electrode NW6 are formed of the same material in the same layer as the capacitance electrode OE, the source line S, and the like. The cross electrode NW7 passes through the contact hole CH10 formed in the insulating layer 13 on the one hand and contacts the connection electrode NW5, and on the other hand passes through the contact hole CH11 formed in the insulating layer 13 and contacts the connection electrode NW6.

The cross electrode NW7 is provided not on the insulating layer 12 but on the insulating layer 13. Compared to the case where the cross electrode NW7 is provided on the insulating layer 12, the load on the gate line G can be reduced.

Also in the display device DSP according to the fourth embodiment configured as described above, the same effect as that of the first embodiment can be obtained. In the manufacturing process of the first substrate SUB1, during the period from the formation of the capacitance electrode OE, the connection electrode NW5, and the connection electrode NW6 to the formation of the cross electrode NW7, the plurality of capacitance electrodes OE arranged in the second direction Y are They are electrically insulated from each other. Since the cross electrode NW7 can be formed and the capacitance wiring CW can be completed in a state where the plurality of capacitance electrodes OE arranged in the second direction Y are not electrically connected, it is possible to prevent the capacitance from being destroyed due to the ESD. it can.

(Fifth Embodiment)
Next, a display device DSP according to the fifth embodiment will be described. FIG. 19 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the fifth embodiment.
As shown in FIG. 19, the display device DSP of the fifth embodiment is different from the third embodiment in that the display device DSP includes a cross electrode OEd instead of the cross electrode OEc and the configuration of the connection wiring NW. It's different.

The capacitance electrode OE has a first capacitance electrode OEa, a second capacitance electrode OEb, and a cross electrode OEd. The intersecting electrode OEd intersects the source line S and is located at a distance from each of the first segment SEa and the second segment SEb. The cross electrode OEd overlaps the first capacitance electrode OEa and the second capacitance electrode OEb, respectively.

In the description of FIG. 19, of the three pixels PX arranged in the first direction X, the capacitance electrode OE of the central pixel PX will be simply referred to as the capacitance electrode OE, and the capacitance electrode OE of the pixel PX at the left end will be referred to as another capacitance. It is referred to as an electrode OE, and the capacitance electrode OE of the pixel PX at the right end is referred to as a third capacitance electrode OE. The other capacitance electrode OE is adjacent to the first capacitance electrode OEa of the capacitance electrode OE. The third capacitance electrode OE is adjacent to the second capacitance electrode OEb of the capacitance electrode OE, and is positioned to sandwich the capacitance electrode OE together with other capacitance electrodes OE.

Each of the connection wiring NWa and the other connection wiring NWb extends in the first direction X, does not intersect with the gate line G, and does not intersect with the source line S. The connection wiring NWa connects the first capacitance electrode OEa of the capacitance electrode OE and another capacitance electrode OE. The connection wiring NWb connects the second capacitance electrode OEb of the capacitance electrode OE and the third capacitance electrode OE. The connection wiring NWa overlaps the first capacitance electrode OEa and the second capacitance electrode OEb of the other capacitance electrode OE, respectively. The connection wiring NWb overlaps the second capacitance electrode OEb and the first capacitance electrode OEa of the third capacitance electrode OE, respectively.
In the present embodiment, the plurality of connection wirings NW and the plurality of capacitance electrodes OE arranged in the first direction X are connected to each other to form the capacitance wiring CW.

20 is a cross-sectional view of the first substrate SUB1 taken along the line XX-XX of FIG.
As shown in FIG. 20, the cross electrode OEd is provided on the insulating layer 13 and covered with the insulating layer 14. The crossing electrode OEd passes through the contact hole CH8 formed in the insulating layer 13 and contacts the first capacitance electrode OEa on the one hand, and contacts the second capacitance electrode OEb through the contact hole CH9 formed in the insulating layer 13 on the other hand. ing. From the above, the crossing electrode OEc electrically connects the first capacitance electrode OEa and the second capacitance electrode OEb.

21 is a cross-sectional view showing the first substrate SUB1 taken along the line XXI-XXI of FIG. As shown in FIG. 21, the connection wiring NWa (NW) is provided on the insulating layer 13 and covered with the insulating layer 14. The connection wiring NWa passes through the contact hole CH6 formed in the insulating layer 13 and contacts the first capacitance electrode OEa of the capacitance electrode OE on the one hand, and passes through the contact hole CH7 formed in the insulating layer 13 on the other hand It is in contact with the second capacitance electrode OEb of the OE. From the above, the connection wiring NWa electrically connects the first capacitance electrode OEa and the second capacitance electrode OEb.

From the above, the cross electrodes OEd and the connection wirings NW are located in layers different from the layers in which the gate lines G and the source lines S are located. The cross electrode OEd and the connection wiring NW are formed of the same material in the same layer as the auxiliary gate electrode AE and the third connection electrode EL3.
In the present embodiment, the plurality of connection wirings NW arranged in the first direction X, the plurality of first capacitance electrodes OEa, the plurality of second capacitance electrodes OEb, and the plurality of crossing electrodes OEd are connected to form a capacitance wiring CW. ing.

Also in the display device DSP according to the fifth embodiment configured as described above, the same effect as that of the third embodiment can be obtained. In the manufacturing process of the first substrate SUB1, a plurality of first lined up in the first direction X is formed during the period from the formation of the first capacitance electrode OEa and the second capacitance electrode OEb to the formation of the cross electrode OEd and the connection wiring NW. The capacitance electrode OEa and the plurality of second capacitance electrodes OEb are electrically insulated from each other. The cross electrode OEd and the connection wiring NW can be formed to complete the capacitance wiring CW in a state where the plurality of first capacitance electrodes OEa and the plurality of second capacitance electrodes OEb arranged in the first direction X are not electrically connected. Therefore, it is possible to prevent the capacity from being destroyed due to the ESD.

(Sixth Embodiment)
Next, the display device DSP according to the sixth embodiment will be described. FIG. 22 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the sixth embodiment.
As shown in FIG. 22, the display device DSP of the sixth embodiment is different from the fifth embodiment in the configuration of the connection wiring NW.

Each connection wiring NW is composed of a connection electrode NW1, a connection electrode NW2, and a cross electrode NW3. The connection electrode NW1 extends in the first direction X, is electrically connected to the first capacitance electrode OEa of the capacitance electrode OE, and extends across the edge of the first segment SEa. The connection electrode NW2 extends in the first direction X, is electrically connected to the second capacitance electrode OEb of the other capacitance electrode OE, and extends across the edge of the second segment SEb. The connection electrode NW1 and the connection electrode NW2 each have a portion that does not overlap the second pixel electrode PE2, and are located at a distance from each other. In the present embodiment, the connection electrode NW1 is formed integrally with the first capacitance electrode OEa of the capacitance electrode OE, and the connection electrode NW2 is formed integrally with the second capacitance electrode OEb of the other capacitance electrode OE.

The cross electrode NW3 is located at a distance from the second pixel electrode PE2, and is overlapped with the connection electrode NW1 and the connection electrode NW2, respectively. In the present embodiment, the plurality of connection wirings NW and the plurality of capacitance electrodes OE arranged in the first direction X are connected to each other to form the capacitance wiring CW.

23 is a cross-sectional view showing the first substrate SUB1 taken along the line XXIII-XXIII in FIG.
As shown in FIG. 23, the cross electrode NW3 is provided on the insulating layer 11. The cross electrode NW3 is formed of the same material as the first segment SEa, the second segment SEb, the gate line G, etc. in the same layer.

The connection electrode NW1 and the connection electrode NW2 are provided on the insulating layer 12. The connection electrode NW1 and the connection electrode NW2 are formed of the same material in the same layer as the capacitance electrode OE, the source line S, and the like. The connection electrode NW1 passes through a contact hole CH6 formed in the insulating layer 12 and is in contact with the cross electrode NW3. The connection electrode NW2 passes through the contact hole CH7 formed in the insulating layer 12 and is in contact with the cross electrode NW3.

Also in the display device DSP according to the sixth embodiment configured as described above, the same effect as that of the fifth embodiment can be obtained.

(Seventh embodiment)
Next, the display device DSP according to the seventh embodiment will be described. FIG. 24 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the seventh embodiment.
As shown in FIG. 24, the display device DSP of the seventh embodiment is different from the third embodiment in that a cross electrode OEd is provided instead of the cross electrode OEc.

The capacitance electrode OE has a first capacitance electrode OEa, a second capacitance electrode OEb, and a cross electrode OEd. The intersecting electrode OEd intersects the source line S and is located at a distance from each of the first segment SEa and the second segment SEb. The cross electrode OEd overlaps the first capacitance electrode OEa and the second capacitance electrode OEb, respectively. The configuration of the capacitance electrode OE is the same as the configuration (FIG. 20) of the capacitance electrode OE of the fifth embodiment. For example, the cross electrode OEd is provided on the insulating layer 13 and covered with the insulating layer 14. The cross electrode OEd is formed of the same material and in the same layer as the auxiliary gate electrode AE and the third connection electrode EL3.

Also in the display device DSP according to the seventh embodiment configured as described above, the same effect as that of the fifth embodiment can be obtained.

(Eighth Embodiment)
Next, the display device DSP according to the eighth embodiment will be described. FIG. 25 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the eighth embodiment.
As shown in FIG. 25, the display device DSP of the eighth embodiment differs from the third embodiment in the configuration of the connection wiring NW.

In the description of FIG. 25, the capacitance electrode OE of the center pixel PX is referred to as a capacitance electrode OE, the capacitance electrode OE of the left end pixel PX is referred to as another capacitance electrode OE, and the capacitance electrode OE of the right end pixel PX is referred to as a third capacitance electrode OE. It is referred to as a capacitance electrode OE. The other capacitance electrode OE is adjacent to the first capacitance electrode OEa of the capacitance electrode OE. The third capacitance electrode OE is adjacent to the second capacitance electrode OEb of the capacitance electrode OE, and is positioned to sandwich the capacitance electrode OE together with other capacitance electrodes OE.

Each of the connection wiring NWa and the other connection wiring NWb extends in the first direction X, does not intersect with the gate line G, and does not intersect with the source line S. The connection wiring NWa connects the first capacitance electrode OEa of the capacitance electrode OE and another capacitance electrode OE. The connection wiring NWb connects the second capacitance electrode OEb of the capacitance electrode OE and the third capacitance electrode OE. The connection wiring NWa overlaps the first capacitance electrode OEa and the second capacitance electrode OEb of the other capacitance electrode OE, respectively. The connection wiring NWb overlaps the second capacitance electrode OEb and the first capacitance electrode OEa of the third capacitance electrode OE, respectively.

In the present embodiment, the plurality of connection wirings NW and the plurality of capacitance electrodes OE arranged in the first direction X are connected to each other to form the capacitance wiring CW. The configuration of the connection wiring NW and the connection relationship between the connection wiring NW and the capacitance electrode OE are the same as those in the fifth embodiment (FIG. 21). For example, the connection wiring NW is provided on the insulating layer 13 and covered with the insulating layer 14. The connection wiring NW is formed of the same material and in the same layer as the auxiliary gate electrode AE and the third connection electrode EL3.

Also in the display device DSP according to the eighth embodiment configured as described above, the same effect as that of the fifth embodiment can be obtained.

(Ninth Embodiment)
Next, a display device DSP according to the ninth embodiment will be described. FIG. 26 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the present ninth embodiment.
As shown in FIG. 26, the display device DSP of the ninth embodiment differs from the third embodiment in the configuration of the connection wiring NW.

Each connection wiring NW is composed of a connection electrode NW1, a connection electrode NW2, and a cross electrode NW3. The connection electrode NW1 extends in the first direction X, is electrically connected to the first capacitance electrode OEa of the capacitance electrode OE, and extends across the edge of the first segment SEa. The connection electrode NW2 extends in the first direction X, is electrically connected to the second capacitance electrode OEb of the other capacitance electrode OE, and extends across the edge of the second segment SEb. The connection electrode NW1 and the connection electrode NW2 each have a portion that does not overlap the second pixel electrode PE2, and are located at a distance from each other. In the present embodiment, the connection electrode NW1 is formed integrally with the first capacitance electrode OEa of the capacitance electrode OE, and the connection electrode NW2 is formed integrally with the second capacitance electrode OEb of the other capacitance electrode OE.

The cross electrode NW3 is located at a distance from the second pixel electrode PE2, and is overlapped with the connection electrode NW1 and the connection electrode NW2, respectively. In the present embodiment, the plurality of connection wirings NW and the plurality of capacitance electrodes OE arranged in the first direction X are connected to each other to form the capacitance wiring CW. The configuration of the connection wiring NW is the same as that of the sixth embodiment (FIG. 23). For example, the connection wiring NW is provided on the insulating layer 11, and is formed of the same material as the first segment SEa, the second segment SEb, the gate line G, and the like in the same layer.

Also in the display device DSP according to the ninth embodiment configured as described above, the same effect as that of the fifth embodiment can be obtained.

(Tenth Embodiment)
Next, the display device DSP according to the tenth embodiment will be described. FIG. 27 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the tenth embodiment. The display device DSP of the tenth embodiment is roughly configured similarly to the display device DSP of the fourth embodiment (FIG. 17). Hereinafter, differences from the configuration of the display device DSP of the fourth embodiment will be described.
As shown in FIG. 27, in the display device DSP of the tenth embodiment, three transistors Tr are connected in parallel between the source line S and the pixel electrode PE.

The pixel PX further includes a third transistor Tr3. The first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 of the third transistor Tr3 extend in the first direction X and are arranged side by side in the second direction Y at intervals. The entire channel regions RC of the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 are overlaid on the same gate line G. In the tenth embodiment, the entire first semiconductor layer SC1, the entire second semiconductor layer SC2, and the entire third semiconductor layer SC3 are overlaid on the same gate line G.

Since the three semiconductor layers SC are superposed on the same gate line G, the gate line G is partially widened. In other words, the gate line G has a protrusion PR that partially protrudes in the second direction Y and faces the second semiconductor layer SC2 and the third semiconductor layer SC3. The protrusions PR are located at intervals in the second pixel electrode PE2.

It is sufficient that the auxiliary gate electrode AE at least overlaps the entire channel region RC of each of the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 in a plan view. In the tenth embodiment, the auxiliary gate electrode AE overlaps the entire first semiconductor layer SC1, the entire second semiconductor layer SC2, and the entire third semiconductor layer SC3.

With the addition of the third semiconductor layer SC3 and the like, the shape of the second pixel electrode PE2, the shape of the second connection electrode EL2, the position of the third connection electrode EL3, etc. are appropriately adjusted.
Also in the display device DSP according to the tenth embodiment configured as described above, the same effect as that of the fourth embodiment can be obtained. It should be noted that, as compared with the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel can be substantially tripled in current while maintaining an allowable current that can flow in one transistor Tr. The electrode PE can be driven.

(Eleventh Embodiment)
Next, the display device DSP according to the eleventh embodiment will be described. FIG. 28 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the eleventh embodiment. The display device DSP of the eleventh embodiment is roughly configured similarly to the display device DSP of the first embodiment (FIG. 5). Hereinafter, differences from the configuration of the display device DSP of the first embodiment will be described.
As shown in FIG. 28, in the display device DSP of the eleventh embodiment, four transistors Tr are connected in parallel between the source line S and the pixel electrode PE.

The pixel PX further includes a third transistor Tr3 and a fourth transistor Tr4. The first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3 of the third transistor Tr3, and the fourth semiconductor layer SC4 of the fourth transistor Tr4 extend in the first direction X and in the second direction Y. They are lined up at intervals. The entire channel regions RC of the first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3, and the fourth semiconductor layer SC4 are overlaid on the same gate line G. In the eleventh embodiment, the entire first semiconductor layer SC1, the entire second semiconductor layer SC2, the entire third semiconductor layer SC3, and the entire fourth semiconductor layer SC4 are overlaid on the same gate line G. ing.

Since the four semiconductor layers SC are superposed on the same gate line G, the gate line G is partially widened. In other words, the gate line G has a protrusion PR that partially protrudes in the second direction Y and faces the second semiconductor layer SC2, the third semiconductor layer SC3, and the fourth semiconductor layer SC4. The protrusions PR are located at intervals in the second pixel electrode PE2.

If the auxiliary gate electrode AE overlaps at least the entire channel region RC of each of the first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3, and the fourth semiconductor layer SC4 in a plan view. Good. In the eleventh embodiment, the auxiliary gate electrode AE overlaps the entire first semiconductor layer SC1, the entire second semiconductor layer SC2, the entire third semiconductor layer SC3, and the entire fourth semiconductor layer SC4. ..

With the addition of the third semiconductor layer SC3 and the fourth semiconductor layer SC4, etc., the shape of the second pixel electrode PE2, the shape of the second connection electrode EL2, the position of the third connection electrode EL3, etc. are adjusted appropriately. There is.
Also in the display device DSP according to the eleventh embodiment configured as described above, the same effect as in the first embodiment can be obtained. In addition, as compared with the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel is substantially quadrupled in current while maintaining the allowable current that can flow in one transistor Tr. The electrode PE can be driven.

(Twelfth Embodiment)
Next, a display device DSP according to the twelfth embodiment will be described. FIG. 29 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the twelfth embodiment. The display device DSP of the twelfth embodiment is roughly configured similarly to the display device DSP of the eleventh embodiment (FIG. 28). Hereinafter, differences from the configuration of the display device DSP of the eleventh embodiment will be described.
As shown in FIG. 29, in the display device DSP of the twelfth embodiment, five transistors Tr are connected in parallel between the source line S and the pixel electrode PE.

The pixel PX further includes a fifth transistor Tr5. The first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3, the fourth semiconductor layer SC4, and the fifth semiconductor layer SC5 of the fifth transistor Tr5 extend in the first direction X and the second direction Y. Are lined up at intervals. The entire channel region RC of each semiconductor layer SC, such as the entire channel region RC of the fifth semiconductor layer SC5, is overlapped with the same gate line G. In the twelfth embodiment, the entire first semiconductor layer SC1, the entire second semiconductor layer SC2, the entire third semiconductor layer SC3, the entire fourth semiconductor layer SC4, and the entire fifth semiconductor layer SC5 are The gate lines G are overlapped with each other.

The protrusion PR further faces the fifth semiconductor layer SC5.
In a plan view, the auxiliary gate electrode AE further overlaps at least the entire channel region RC of the fifth semiconductor layer SC5. In the twelfth embodiment, the auxiliary gate electrode AE includes the entire first semiconductor layer SC1, the entire second semiconductor layer SC2, the entire third semiconductor layer SC3, the entire fourth semiconductor layer SC4, and the fifth semiconductor. It overlaps the entire layer SC5.

With the addition of the fifth semiconductor layer SC5 and the like, the shape of the protrusion PR and the like are appropriately adjusted.
Also in the display device DSP according to the twelfth embodiment configured as described above, the same effect as that of the eleventh embodiment can be obtained. It should be noted that, as compared with the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel can be substantially five times the current while maintaining the allowable current that can flow in one transistor Tr. The electrode PE can be driven.

While some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are also included in the invention described in the claims and the scope equivalent thereto. It is also possible to combine a plurality of embodiments as needed.

For example, in the above-described embodiment, an example is shown in which two, three, four, or five transistors Tr are connected in parallel between the source line S and the pixel electrode PE. However, it is sufficient that two or more transistors Tr are connected in parallel between the source line S and the pixel electrode PE. Therefore, six or more transistors Tr may be connected in parallel between the source line S and the pixel electrode PE.
The transistor Tr may be formed without the auxiliary gate electrode AE.
The semiconductor layer SC may be located between the first base material 1 and the gate line G. When a conductive light-shielding layer exists between the first base material 1 and the semiconductor layer SC, the light-shielding layer may be electrically connected to the gate line G to function as an auxiliary gate electrode.

The semiconductor substrate of the above-described embodiment is applicable not only to the above-described first substrate SUB1 but also to various semiconductor substrates.
Further, the display device DSP of the above-described embodiment is applicable not only to the electrophoretic display device described above, but also to various display devices. For example, the display device DSP may be a liquid crystal display device. In that case, the display function layer DL is a liquid crystal layer. The liquid crystal layer may use, for example, polymer dispersed liquid crystal (PDLC).

DSP... Display device, PNL... Display panel, DA... Display area, NDA... Non-display area,
SUB1... First substrate, 1... First base material, PX... Pixel, G... Gate line, S... Source line,
Tr1... 1st transistor, Tr2... 2nd transistor, SC1... 1st semiconductor layer,
SC2... second semiconductor layer, SC3... third semiconductor layer, SC4... fourth semiconductor layer,
SC5... Fifth semiconductor layer, R1... First region, R2... Second region, RC... Channel region,
AE... Auxiliary gate electrode, PE... Pixel electrode, PE1... First pixel electrode,
PE2... second pixel electrode, SEa... first segment, SEb... second segment,
OE...capacitance electrode, OEa...first capacitance electrode, OEb...second capacitance electrode, OEc...cross electrode,
NW, NWa, NWb... connection wiring, NW1, NW2... connection electrode, NW3... crossing electrode,
CW... capacitance wiring, C1... first capacitance, C2... second capacitance, SUB2... second substrate,
2... 2nd base material, CE... Counter electrode, DL... Display function layer, DOa... 1st domain,
DOb... second domain, BL... boundary line, WI... width, L... channel length, W... channel width,
AX1... Long axis, AX2... Short axis, X... First direction, Y... Second direction, Z... Third direction.

Claims (15)

A first substrate,
A gate line positioned above the first base material;
A source line located above the first substrate,
An insulating film located above the gate line and below the source line;
A first pixel electrode positioned above the first base material, the gate line, and the source line;
A first transistor and a second transistor which are located above the first base material and electrically connected in parallel between the source line and the first pixel electrode;
The first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor are electrically connected to the first region electrically connected to the source line and the first pixel electrode, respectively. A second region and a channel region between the first region and the second region,
The first semiconductor layer and the second semiconductor layer are in contact with a first surface of the insulating film on the source line side,
The entire channel region of each of the first semiconductor layer and the second semiconductor layer is overlapped with the gate line.
Semiconductor substrate. The first semiconductor layer and the second semiconductor layer each have a major axis in a direction in which the gate line extends,
The first semiconductor layer and the second semiconductor layer are entirely overlapped with the gate line,
The semiconductor substrate according to claim 1. The width of the gate line is larger than the sum of the length of the minor axis of the first semiconductor layer and the length of the minor axis of the second semiconductor layer,
The semiconductor substrate according to claim 2. The first semiconductor layer and the second semiconductor layer are arranged in the width direction of the gate line,
The semiconductor substrate according to claim 3. A second pixel electrode located between the first base material and the first pixel electrode and electrically connected to the first pixel electrode;
A capacitive electrode that is located between the first pixel electrode and the second pixel electrode and is capacitively coupled to each of the first pixel electrode and the second pixel electrode;
When seen in a plan view, the entire capacitance electrode is located inside the first pixel electrode and inside the second pixel electrode,
The semiconductor substrate according to claim 1. Another capacitance electrode located with the gate line sandwiched together with the capacitance electrode,
Further comprising a connection wiring connecting the capacitance electrode and the other capacitance electrode,
The source line intersects the gate line,
The connection wiring intersects the gate line and does not intersect the source line,
The semiconductor substrate according to claim 5. The gate line and the second pixel electrode are formed of the same material and located in the same layer,
The source line, the capacitance electrode, the other capacitance electrode, and the connection wiring are formed of the same material and located in the same layer,
The capacitance electrode, the other capacitance electrode, and the connection wiring are integrally formed,
The semiconductor substrate according to claim 6. Another capacitance electrode positioned with the source line sandwiched together with the capacitance electrode,
Further comprising a connection wiring connecting the capacitance electrode and the other capacitance electrode,
The source line intersects the gate line,
The connection wiring intersects the source line and does not intersect the gate line,
The semiconductor substrate according to claim 5. A second pixel electrode located between the first base material and the first pixel electrode;
Further comprising a capacitive electrode,
The source line intersects with the gate line and is located on a boundary line between the first domain and the second domain;
The second region and the channel region of the first semiconductor layer are located in the first domain,
The second region and the channel region of the second semiconductor layer are located in the second domain,
The second pixel electrode is
A first segment located in the first domain and electrically connected to the first pixel electrode;
A second segment located in the second domain and electrically connected to the first pixel electrode,
The capacitance electrode is
A first capacitance electrode located between the first pixel electrode and the first segment in the first domain, and capacitively coupled to each of the first pixel electrode and the first segment;
A second capacitance electrode located between the first pixel electrode and the second segment in the second domain, and capacitively coupled to each of the first pixel electrode and the second segment;
A crossing electrode that intersects the source line and electrically connects the first capacitance electrode and the second capacitance electrode,
The semiconductor substrate according to claim 1. Another capacitance electrode adjacent to the first capacitance electrode,
A third capacitance electrode that is adjacent to the second capacitance electrode and is positioned with the other capacitance electrode sandwiching the capacitance electrode;
Connection wiring connecting the first capacitance electrode and the other capacitance electrode,
And another connection wiring connecting the second capacitance electrode and the third capacitance electrode,
The connection wiring and the other connection wiring do not intersect the gate line and do not intersect the source line, respectively.
The semiconductor substrate according to claim 9. If the channel length and the channel width in the channel regions of the first semiconductor layer and the second semiconductor layer are L and W, respectively,
W/L≦0.75,
The semiconductor substrate according to claim 1. The first semiconductor layer and the second semiconductor layer are each formed of an oxide semiconductor,
The semiconductor substrate according to claim 11. Further comprising an auxiliary gate electrode electrically connected to the gate line and sandwiching the first semiconductor layer and the second semiconductor layer together with the gate line,
In a plan view, the auxiliary gate electrode at least overlaps the entire channel region of both the first semiconductor layer and the second semiconductor layer,
The semiconductor substrate according to claim 1. A first base material, a gate line located above the first base material, a source line located above the first base material, a source line located above the gate line, and a position located below the source line An insulating film, a first pixel electrode located above the first base material, the gate line, and the source line, and an electrical connection between the source line and the first pixel electrode located above the first base material. A semiconductor substrate having a first transistor and a second transistor connected in parallel with one pixel electrode;
A counter substrate including a second base material facing the first pixel electrode, and a counter electrode located between the second base material and the first pixel electrode and facing the first pixel electrode;
A display function layer located between the first pixel electrode and the counter electrode, to which a voltage applied between the first pixel electrode and the counter electrode is applied,
The first semiconductor layer of the first transistor and the second semiconductor layer of the second transistor are electrically connected to the first region electrically connected to the source line and the first pixel electrode, respectively. A second region and a channel region between the first region and the second region,
The first semiconductor layer and the second semiconductor layer are in contact with a first surface of the insulating film on the source line side,
The entire channel region of each of the first semiconductor layer and the second semiconductor layer is overlapped with the gate line.
Display device. The display functional layer is an electrophoretic layer,
The display device according to claim 14.

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