JP4722566B2 - LCD panel - Google Patents

Description

  The present invention relates to a liquid crystal display panel having a thin film transistor substrate in which a gate signal line and a drain signal line are orthogonal to each other on a thin film transistor for driving a pixel electrode.

  Currently, there are two types of liquid crystal display panels: passive matrix liquid crystal display panels and active matrix liquid crystal display panels. Among these, active matrix liquid crystal display panels with improved response speed, viewing angle, and contrast are the mainstream. This active matrix liquid crystal display panel includes a light transmissive color filter substrate in which a colored resin is formed for each pixel, and a light transmissive thin film transistor substrate in which a thin film transistor or a nonlinear element is formed in each pixel. It is formed by sandwiching layers.

  A plurality of thin film transistors are formed on the thin film transistor substrate of the liquid crystal display panel by photolithography. In order to improve the quality of the liquid crystal display panel by suppressing display unevenness of the liquid crystal display panel and to improve the yield of the liquid crystal display panel in the plurality of thin film transistors, various measures are taken so that the characteristics of each thin film transistor become the same characteristics. Has been made.

  A technique has been proposed in which two thin film transistors are provided for one pixel so that the characteristics of the thin film transistors on the thin film transistor substrate are substantially the same (for example, see Patent Document 1).

In addition, the gate electrode connected to the external gate signal line and the source electrode connected to the external source signal line are orthogonal to each other, and each thin film transistor is alternately arranged on the left and right in each row with respect to the source signal line. A technique has been proposed in which the characteristics of the thin film transistors on the thin film transistor substrate are made substantially the same (see, for example, Patent Document 2).
JP 05-251700 A JP-A-10-090718

  By the way, the pattern of the thin film transistor is locally shifted due to dust in the manufacturing process by photolithography. When the pattern of the thin film transistor is deviated, characteristics such as parasitic capacitance in each thin film transistor of the thin film transistor substrate are locally abruptly changed, and display unevenness occurs in the liquid crystal display panel.

  The present invention has been made in view of these points, and an object of the present invention is to provide a liquid crystal display panel in which the parasitic capacitances of the thin film transistors of the thin film transistor substrate are substantially the same.

  In the present invention, in order to solve the above problems, as illustrated in FIG. 2, in a liquid crystal display panel having a thin film transistor substrate in which a gate signal line 11 and a drain signal line 13 are orthogonal to each other on a thin film transistor 10 for driving a pixel electrode. The drain electrode 14 on the gate electrode 12 has a first drain electrode portion 14 a connected to the drain signal line 13 and a second drain electrode portion 14 b extending in the outward direction. A liquid crystal display panel is provided in which the first drain electrode portion 14 a and the second drain electrode portion 14 b on the gate electrode 12 are point-symmetric from the center of the thin film transistor 10.

  According to such a liquid crystal display panel, even if the gate electrode 12 is formed in a shifted manner, or the drain electrode 14 and the source electrode 15 are formed in a shifted manner, it depends on the gate electrode 12 and the drain electrode 14 of each thin film transistor 10. Since the parasitic capacitance does not change, the parasitic capacitance in each thin film transistor 10 of the thin film transistor substrate can be made substantially the same.

  In the present invention, the first drain electrode portion connected to the drain signal line on the gate electrode and the second drain electrode portion extending outwardly on the gate electrode are point-symmetric from the center of the thin film transistor. To be.

  In this way, even if the gate electrode is formed in a shifted manner or the drain electrode and the source electrode are formed in a displaced manner, the parasitic capacitance due to the gate electrode and the drain electrode of each thin film transistor does not change. The parasitic capacitance in each thin film transistor can be made substantially the same. Therefore, display unevenness of the liquid crystal display panel can be suppressed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, a liquid crystal display panel according to an embodiment of the present invention will be described. FIG. 1 is a diagram showing a liquid crystal display panel.

  In the liquid crystal display panel, a thin film transistor substrate 1 in which a thin film transistor (not shown) is formed for each pixel and a color filter substrate 3 in which a colored resin is formed for each pixel are formed with a liquid crystal layer 2 interposed therebetween. .

  The thin film transistor substrate 1 having a thin film transistor (not shown) for each pixel drives a transparent electrode (not shown) of the color filter substrate 3 and a transparent electrode (not shown) of the thin film transistor substrate 1 corresponding to each pixel. To adjust the brightness of each pixel.

  The liquid crystal layer 2 having a plurality of liquid crystal molecules (not shown) is irradiated with light from a backlight unit (not shown) according to the voltage difference between the transparent electrode of the color filter substrate 3 and the transparent electrode of the thin film transistor substrate 1. Whether to pass through the color filter substrate 3 is determined. For example, when the voltage difference is equal to or larger than a predetermined voltage difference, the light irradiated from the backlight unit in response to the liquid crystal molecules passes through the color filter substrate 3. If the voltage difference is smaller than the predetermined voltage difference, the liquid crystal molecules do not respond and the light irradiated from the backlight unit is not passed through the color filter substrate 3.

  The color filter substrate 3 having a colored resin for each pixel enables display of various colors by combining the three primary colors of light. By adjusting the brightness of each primary color by the colored resin of a plurality of pixels, it is possible to display various colors and serve as a color filter.

  In such a liquid crystal display panel, the transparent electrode of the color filter substrate 3 and the transparent electrode of the thin film transistor substrate 1 corresponding to each pixel are driven by the thin film transistor for each pixel. Depending on the voltage difference resulting from the driving of each transparent electrode, whether or not the light emitted from the backlight unit is allowed to pass through the color filter substrate 3 is determined by the liquid crystal molecules for each pixel. Is adjusted. The combination of the three primary colors of light using the colored resin of the plurality of pixels determines the color at a predetermined location, and these can be collected to display various images.

Next, a plurality of thin film transistors formed on the thin film transistor substrate 1 will be described. FIG. 2 shows a thin film transistor.
The gate electrode 12 connected to the gate signal line 11 is in contact with the channel 16. The channel 16 is sandwiched between a drain electrode 14 connected to the drain signal line 13 and a source electrode 15 connected to a transparent electrode (not shown). The drain electrode 14 has a first drain electrode portion 14 a connected to the drain signal line 13 and a second drain electrode portion 14 b extending outward. The gate signal line 11 and the drain signal line 13 are connected to a gate driver circuit (not shown) and a drain driver circuit (not shown), respectively, in regions where the thin film transistors 10 are not formed in a matrix. ing.

  The thin film transistor 10 includes a gate signal line 11, a gate electrode 12, a gate insulating film (not shown), a channel 16, and a drain signal with respect to the thin film transistor substrate 1, which is a transparent substrate, by photolithography using Al, Mo, or the like. A line 13, a drain electrode 14, a source electrode 15, an insulating film (not shown), and a transparent electrode are formed in this order. The gate signal line 11 and the gate electrode 12 are simultaneously formed of the same material, and the drain signal line 13, the drain electrode 14 and the source electrode 15 are simultaneously formed of the same material. A plurality of thin film transistors 10 are formed in a matrix.

  Here, the first drain electrode portion 14a and the gate electrode 12 overlap to form a parasitic capacitance CGD1, and the parasitic capacitance CGD1 is proportional to the overlapping area. Similarly, the second drain electrode portion 14b and the gate electrode 12 overlap to form a parasitic capacitance CGD2, and the parasitic capacitance CGD2 is proportional to the overlapping area. The total parasitic capacitance CGD of the parasitic capacitance CGD1 and the parasitic capacitance CGD2 transmits to the drain electrode 14 the potential fluctuation between the sharp rise and fall of the gate signal potential as noise with respect to the gate electrode 12. . Due to the presence of the noise, the drain signal potential written to the source electrode 15 fluctuates, and the written source signal potential differs from the written drain signal potential.

  The second drain electrode portion 14b, which is a redundant portion of the drain electrode 14, increases the redundancy of the drain electrode 14, and even if the pattern of the thin film transistor 10 is shifted, the gate electrode 12 and the drain electrode in each thin film transistor 10 of the thin film transistor substrate 1 The parasitic capacitances CGD corresponding to the area where 14 and 14 overlap are substantially the same. Specifically, in the second drain electrode portion 14b having a length of 5 μm, the gate electrode 12 is formed with a shift of about 5 / √2 μm, or the drain electrode 14 and the source electrode 15 are shifted by about 5 / √2 μm. Even if formed, the parasitic capacitance CGD in each thin film transistor 10 of the thin film transistor substrate 1 is made substantially the same. That is, in the second drain electrode portion 14b, in each thin film transistor 10, the potential variation caused by the gate electrode 12 of the drain signal potential written to the source electrode 15 varies substantially the same.

Next, a case where the pattern of the thin film transistor 10 is shifted will be described. FIG. 3 is a diagram illustrating a thin film transistor having a shifted pattern.
Here, it is assumed that in the manufacturing process of the liquid crystal display panel, dust having a diameter of several tens of μm is placed on the photostage, and further, the thin film transistor substrate 1 is placed thereon.

  The portion of the thin film transistor substrate 1 corresponding to dust is bent and rises locally. When a plurality of thin film transistors 10 are formed by performing photolithography on the thin film transistor substrate 1 that is locally bent in this manner, the hatched portion in FIG. 2 and the hatched portion in FIG. 3 in the thin film transistor 10 corresponding to the bent portion. And the gate electrode 12 is formed with a shift of about 2 μm to 3 μm, or the drain electrode 14 and the source electrode 15 are formed with a shift of about 2 μm to 3 μm.

  In the thin film transistor substrate 1 having a plurality of thin film transistors 10, it is desirable that each thin film transistor 10 is patterned almost uniformly, and it is desirable that the parasitic capacitance CGD in each thin film transistor 10 is substantially the same. In this case, in each thin film transistor 10, the potential fluctuation caused by the gate electrode 12 of the drain signal potential written to the source electrode 15 varies substantially the same, and the potential fluctuation caused by the gate electrode 12 of the source signal potential is also almost equal. The potential fluctuates the same.

  In the thin film transistor 10 in which the pattern is shifted, the drain electrode 14 of the thin film transistor 10 has a first drain electrode portion 14 a connected to the drain signal line 13 and a second drain electrode portion 14 b extending outward. These portions are point-symmetric from the center of the thin film transistor 10. Therefore, when the gate electrode 12 is shifted, the second drain electrode portion 14b which is a redundant portion of the drain electrode 14 increases the parasitic capacitance CGD2 and increases the parasitic capacitance CGD1 even if the parasitic capacitance CGD1 decreases. However, the parasitic capacitance CGD2 decreases accordingly. Therefore, even if the gate electrode 12 is shifted in the thin film transistor 10, the total parasitic capacitance CGD of the parasitic capacitance CGD1 and the parasitic capacitance CGD2 does not change. Similarly, when the drain electrode 14 and the source electrode 15 are displaced, even if the parasitic capacitance CGD1 is decreased by the second drain electrode portion 14b, the parasitic capacitance CGD2 is increased correspondingly, and the parasitic capacitance CGD1 is increased accordingly. The parasitic capacitance CGD2 decreases. Therefore, even if the drain electrode 14 and the source electrode 15 are displaced in the thin film transistor 10, the total parasitic capacitance CGD of the parasitic capacitance CGD1 and the parasitic capacitance CGD2 does not change.

  In this way, even if the gate electrode 12 is formed with a deviation of about 2 μm to 3 μm in the bent portion of the thin film transistor substrate 1 due to dust, or the drain electrode 14 and the source electrode 15 are formed with a deviation of about 2 μm to 3 μm, Since the total parasitic capacitance CGD of the parasitic capacitance CGD1 and the parasitic capacitance CGD2 of each thin film transistor 10 does not change, the parasitic capacitance CGD in each thin film transistor 10 of the thin film transistor substrate 1 becomes almost the same, and the source signal of the source electrode 15 of each thin film transistor 10 The potential variation can be made substantially the same. Therefore, display unevenness of the liquid crystal display panel can be suppressed, and the quality of the liquid crystal display panel can be improved.

  Even if the gate electrode 12 is formed with a deviation of about 2 μm to 3 μm or the drain electrode 14 and the source electrode 15 are formed with a deviation of about 2 μm to 3 μm in the bent portion of the thin film transistor substrate 1 due to dust, each thin film transistor 10 Since the parasitic capacitance CGD does not change, dust in the manufacturing process by photolithography does not cause a decrease in the yield of the liquid crystal display panel.

It is a figure which shows a liquid crystal display panel. It is a figure which shows a thin-film transistor. It is a figure which shows the thin-film transistor from which the pattern shifted | deviated.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Thin-film transistor 11 Gate signal line 12 Gate electrode 13 Drain signal line 14 Drain electrode 14a 1st drain electrode part 14b 2nd drain electrode part 15 Source electrode 16 Channel

Claims (5)

In a liquid crystal display panel having a thin film transistor substrate in which a gate signal line and a drain signal line are orthogonal to each other on a thin film transistor that drives a pixel electrode,
The gate electrode has two isosceles trapezoidal projections projecting in a direction perpendicular to the gate signal line and in an opposite direction from the gate signal line in the vicinity of the intersection of the gate signal line and the drain signal line It has an octagon shape with a part,
Drain electrode on the gate electrode, it has a second drain electrode portion extending outwardly of the gate electrode over the first drain electrode portion connected to the drain signal line area of the gate electrode And
The two isosceles bases constituting the gate electrode, wherein the first drain electrode part on the gate electrode and the second drain electrode part on the gate electrode are point-symmetric from the center of the thin film transistor. A liquid crystal display panel, characterized in that the liquid crystal display panel is provided across the opposing leg portions of the shape protrusions .   The liquid crystal display panel according to claim 1, wherein a length of the first drain electrode portion on the gate electrode and the second drain electrode portion on the gate electrode is 5 μm or more. A television receiver using the liquid crystal display panel according to claim 1 . A computer using the liquid crystal display panel according to claim 1 . A cellular phone device using the liquid crystal display panel according to claim 1 .

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