JPH0122738B2 - - Google Patents
Info
- Publication number
- JPH0122738B2 JPH0122738B2 JP4293484A JP4293484A JPH0122738B2 JP H0122738 B2 JPH0122738 B2 JP H0122738B2 JP 4293484 A JP4293484 A JP 4293484A JP 4293484 A JP4293484 A JP 4293484A JP H0122738 B2 JPH0122738 B2 JP H0122738B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- pattern
- deposited
- opening
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4293484A JPS60189241A (ja) | 1984-03-08 | 1984-03-08 | 段差の被覆方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4293484A JPS60189241A (ja) | 1984-03-08 | 1984-03-08 | 段差の被覆方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60189241A JPS60189241A (ja) | 1985-09-26 |
| JPH0122738B2 true JPH0122738B2 (enExample) | 1989-04-27 |
Family
ID=12649838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4293484A Granted JPS60189241A (ja) | 1984-03-08 | 1984-03-08 | 段差の被覆方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189241A (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01107557A (ja) * | 1987-10-21 | 1989-04-25 | Agency Of Ind Science & Technol | 配線の形成方法 |
| JPH0680736B2 (ja) * | 1987-10-21 | 1994-10-12 | 工業技術院長 | 配線の形成方法 |
-
1984
- 1984-03-08 JP JP4293484A patent/JPS60189241A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60189241A (ja) | 1985-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0191057B1 (en) | Electrical contact in semiconductor devices | |
| US4720908A (en) | Process for making contacts and interconnects for holes having vertical sidewalls | |
| US4523975A (en) | Integrated circuit planarizing process | |
| JPH11500272A (ja) | 電気的に導電性を有するコンタクトプラグの形成に関する半導体の製造方法 | |
| JPS6199352A (ja) | 平面化された接点を有する半導体デバイスの製造方法 | |
| US6232663B1 (en) | Semiconductor device having interlayer insulator and method for fabricating thereof | |
| JPH02183534A (ja) | 集積デバイス中に接点を形成するために絶縁層を通してテーパー状のホールを形成する方法 | |
| US4486464A (en) | Method of making planarizing non-conductive layers employing conductive metals | |
| US6218266B1 (en) | Method of fabricating electronic devices of the type including smoothing process using polishing | |
| JP2618460B2 (ja) | 電気接続体の形成方法 | |
| US4764483A (en) | Method for burying a step in a semiconductor substrate | |
| JPH02143527A (ja) | 配線形成方法 | |
| US5940730A (en) | Method of forming a contact hole of a semiconductor device | |
| JPS60189241A (ja) | 段差の被覆方法 | |
| JPS6332260B2 (enExample) | ||
| US5324536A (en) | Method of forming a multilayered structure | |
| KR0127271B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
| JP2900888B2 (ja) | 半導体装置の製造方法 | |
| JPS6052043A (ja) | 配線構造の製造方法 | |
| JPS61179532A (ja) | コンタクト電極の形成方法 | |
| JPS60233840A (ja) | 段差の被覆方法 | |
| JPH0552057B2 (enExample) | ||
| JPS6360551A (ja) | Mim構造キヤパシタ | |
| JPS6146051A (ja) | 配線方法 | |
| JPS61120417A (ja) | コンタクト電極の形成方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |