JPH0122738B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for covering steps, and in particular, to forming a conductive film on a surface with a steep step such as a multilayer wiring or the side surface of a minute opening. It is about the method.

(Prior Art and Its Disadvantages) For example, in the case of wiring in a semiconductor device, a conductive film is deposited on a base insulating film having fine openings. At this time, if the conventional sputtering method or vapor deposition method is used, the wiring tends to break or become thin at the shoulder part of the step of the opening.
The manufacturing yield and reliability of LSIs had decreased significantly. In order to prevent these drawbacks, the side surfaces of minute openings are now tapered and sloped so that the conductive film can be coated uniformly. Giving a slope to the LSI impedes high integration of LSIs and is not a preferable improvement method. Therefore, methods have been proposed for depositing a conductive film with good step coverage on steep and deep steps, and one of these methods is the aluminum low pressure CVD method. MJ has shown that a film with good step coverage can be formed by depositing an aluminum film using the low pressure CVD method.
Cooke et al., Solid State Technology, Volume 25, No. 12
No. 62-65. However, in a multilayer wiring structure, even if a film forming method with good step coverage is used, there is a drawback that the pattern dimensional processing accuracy becomes worse as the steps are accumulated in the upper layers.

When depositing a conductor film over the fine openings in a multilayer thin film structure such as LSI or VLSI wiring, one important thing is to cover the fine openings without causing microcracks in the conductor film. One is to fill the minute openings, and the other is to make the surface flat after a conductive film is deposited to fill the minute openings. especially
These two factors are extremely important for increasing the integration and multilayering of LSIs and achieving high reliability.

The bias sputtering method is known as a method for improving film quality and for depositing a film flatly on an uneven substrate without causing microcracks in the deposited film. In the bias sputtering method, the deposition of the target material on the substrate and the etching of the deposited film on the substrate by reverse sputtering proceed simultaneously.
Effectively, a deposition or etching rate equal to the difference between deposition and etching can be obtained. In addition, the deposition rate and etching rate each independently depend on the angle of the slope of the substrate underlying film, and the effective deposition rate also varies depending on the slope angle of the underlying film. It is possible to deposit a somewhat flat conductor film on a surface with steps. The planarization is performed, for example, as shown in FIGS. 1a to 1d.
This figure was published by CYTing et al. in the Journal of
Journal of Vacuum Science and Technology
This model is basically the same as the model described in vol. 15, no. 3, pages 1105 to 1112 of ``Technology'' magazine. Figure 1 a shows a silicon substrate with a flat surface.
A state in which an insulating film 102 such as a silicon oxide film is deposited on 101 and an opening 103 is formed through a normal photoresist process and a dry etching process is shown. Next, in FIG. 1b, a conductor film 1 is formed using a bias sputtering method under sputtering conditions that do not cause shadow effects.
04 is deposited to a thickness approximately equal to that of the insulating film 102. At this point, the cross section of the conductive film 104 deposited on the insulating film 102 has a trapezoidal shape with the bottom base at the interface with the insulating film and a taper angle θ determined by the bias voltage. Furthermore, the first
Figure c shows a state in which the conductive film 104 was further deposited under the same sputtering conditions. The inclined surface of the conductor film 104 maintains the taper angle θ and the opening 10
3 is formed on the extension of the broken line extending from the vicinity of the shoulder of the insulating film step caused by the formation of the insulating film step. Therefore, if the conductive film 104 is continued to be deposited under the same sputtering conditions, the length of the upper base of the trapezoid will gradually decrease and eventually disappear completely as shown in FIG. 1d, achieving flattening. At this time, the thickness of the conductor film on the insulating film is given by W·tanθ/2, where W is the width of the insulating film between the openings. From the perspective of flattening, θ=
The most desirable value is 0°, but when attempting to deposit and planarize a conductor film under a single sputtering condition as shown in Figures 1a to d, the value of θ is usually 30° or more. For example, when the value of θ is 30° and the value of W is 20 μm, the conductor film is usually too thick, about 6 μm, in order to obtain the flat surface shown in FIG. 1d. For this reason, after depositing the conductor film by high frequency bias sputtering method until the state shown in Fig. 1 d,
A method of etching back a conductive film using reverse sputtering has been proposed. However, in the case of etching by reverse sputtering, the etching speed is extremely slow and the sum of the time for depositing the conductor film and the time for etching back becomes enormous, making it impractical. As described above, the disadvantage of planarization using the bias sputtering method is that the area of the opening is small and when the area on the step to be flattened is large, a long time of several tens of hours is required.
Further, it is necessary to deposit a film with a thickness greater than that required in a multilayer thin film structure.

(Objective of the Invention) The object of the present invention is to solve the problems of the conventional method of covering steps as described above, and in particular, to solve the problems of the conventional method of covering steps. It is an object of the present invention to provide a method for covering steps that is flattened and filled with a conductive film in a short time.

(Structure of the Invention) According to the present invention, in a method for covering a step in which a substrate having an insulating film pattern formed on its surface is filled with a conductive film using a bias sputtering method, a first step of embedding the pattern up to part of the height of the pattern under sputtering conditions that do not cause microcracks in the conductor film and do not form grooves along the bottom of the pattern step in the underlying substrate; The unembedded portion is determined by determining whether there are no microcracks in the adhered conductor film and the thickness of the adhered conductor film on the flat surface between the patterns is equal to the height of the pattern step and the adhered conductor film on the flat surface above the pattern step. There is obtained a method for covering a step, which is characterized by including a second step of embedding using sputtering conditions that are approximately equal to the sum of the thickness of the film.

(Experimental facts on which the invention is based) The present invention is based on detailed experiments conducted by the inventors on the high frequency bias sputtering method and the results of the experiments. The inventors have continued to experiment with the high-frequency bias sputtering method using aluminum, molybdenum, impurity-doped polycrystalline silicon, silicide, etc. as the step covering material, and silicon oxide film, silicon nitride film, etc. as the insulating film. However, I came to know the following facts.

To explain the case where molybdenum is used as the step covering material and silicon oxide film is used as the insulating film,
A silicon substrate with a silicon oxide film opening having a steep side surface of 2.5 μm in diameter and 1 μm in depth was formed on the molybdenum side of the target under sputtering conditions with an argon gas pressure of 3 mTorr and an electrode distance of 95 mm. When applying a power density of 5.7 W/cm ² and changing the high frequency (13.56 MHz) bias voltage applied to the substrate side as a parameter from 0 V to -700 V in 100 V increments, when the high frequency bias voltage is below -300 V, due to the shadow effect. It was not possible to fill the inside of the opening in the deposited film without causing microcracks, but when the voltage exceeds -400V, it becomes possible to fill the inside of the opening in the molybdenum film without causing microcracks. Furthermore, when the voltage is increased to 600V, as shown in the schematic cross-sectional view of FIG. The thickness of the molybdenum film was approximately 1.5 times that of the molybdenum film deposited on the flat surface of the pattern. This phenomenon is thought to be due to the reverse sputtering of the molybdenum film deposited on the side surfaces inside the opening and re-adhering to the flat surface inside the opening.

Therefore, the ratio between the thickness of the molybdenum film deposited on the flat surface inside the opening and the thickness of the molybdenum film deposited on the flat surface above the step of the pattern can be adjusted appropriately by adjusting the high frequency bias voltage or other sputtering conditions. By doing so, it is possible to increase the number by one or more times.
For example, when a 1.3 μm molybdenum film is deposited on a flat surface on a pattern step under sputtering conditions with a high frequency bias voltage of -600 V, approximately 2 μm of film is deposited inside the opening, and the step on the conductor film surface is 0.3 μm. decreases to However, at a high frequency bias voltage of -600V, a groove 204 was formed along the bottom of the step in the underlying silicon substrate as shown in FIG. Therefore, it has been found that at the initial stage of film deposition, it is necessary to use relatively low high frequency bias voltage conditions that do not cause grooves to form along the bottoms of the steps in the underlying silicon substrate.

(Example) Hereinafter, the present invention will be described with reference to drawings showing examples. FIGS. 3a to 3c are schematic sectional views sequentially showing one embodiment step by step.

Figure 3a shows a silicon oxide film 302 with a thickness of about 1 μm on a single crystal silicon substrate 301 with a flat surface.
After being deposited using the CVD method, the diameter is
A state in which a 2.5 μm opening is formed is shown.

Next, as shown in FIG. 3b, sputtering conditions (argon gas pressure) were used so that the molybdenum film was deposited within the opening without microcracks and no grooves were formed along the bottom of the step in the underlying silicon substrate.
After the molybdenum film 303 was formed by high-frequency bias sputtering at a temperature of 3 mTorr, a distance between electrodes of 95 mm, a power density of 5.7 W/cm ² on the target side, and a high-frequency bias voltage of -400 V, the bias voltage was set to -700 V, an insulating film was formed on the underlying silicon substrate. It is applied to a thickness (approximately 0.1 μm) that does not create a groove along the bottom of the step.

Next, as shown in FIG. 3c, the film deposition speed of the molybdenum film deposited on the flat surface inside the opening is approximately 2 times the film deposition speed of the molybdenum film deposited on the flat surface above the step of the opening. Sputtering conditions that double the amount (argon gas pressure 3mTorr, distance between electrodes 95mm, target side power density 5.7W/cm ² , high frequency bias voltage -700V)
Molybdenum film 30 was formed using high frequency bias sputtering.
4 was applied to the flat surface on the step of the opening by about 1 μm.
Under these conditions, a molybdenum film of approximately 2 μm is deposited inside the opening, a molybdenum film of approximately 1 μm is deposited on the flat surface on the step of the opening, and a molybdenum film of approximately 1 μm is deposited on the silicon oxide film with the opening. The membrane becomes almost flat.

In the above embodiments, a molybdenum film was deposited, but there is no need to limit it to this, and other metals such as aluminum, polycrystalline silicon doped with impurities,
Alloys such as silicide can also be used. Further, in the embodiments described above, only the bias voltage was used as a parameter, but there is no need to limit it to this, and other sputtering conditions such as the target side power density and the distance between electrodes may be used as parameters. Lowering the power density on the target side has the same effect as increasing the bias voltage. Increasing the distance between the electrodes has the same effect as increasing the bias voltage.

Although a high frequency bias was used in the above embodiment, a direct current bias may also be used.

(Effects of the Invention) As explained above, the present invention improves the deposition speed of the conductor film onto the flat surface of the opening and the deposition speed of the conductor film onto the flat surface above the step of the opening. This is carried out by a high frequency bias sputtering method in which the ratio of 1 to 1 is increased by adjusting the high frequency bias voltage or other sputtering conditions. As a result, when the area of the opening is small and the area of the step to be flattened is large using the high-frequency bias sputtering method, the sputtering time can be significantly shortened (by at least one order of magnitude). Furthermore, the advantage of being able to form a film within the same vacuum system can be maintained.

As explained above, according to the present invention, even an opening with a steep side surface can be filled with a conductive film without producing a shadow effect or causing microcracks in the deposited conductive film, and can be filled with a conductive film on a pattern of an insulating film. The conductive film can be formed so that the surface is flat. As a result, in the case of a multilayer wiring structure, it is possible to avoid disconnections in the wiring formed in the upper layer, poor contact, and deterioration of dimensional processing accuracy, and when used in LSI, reliability and integration can be dramatically improved. Can be done.

[Brief explanation of drawings]

Figures 1 a to d are film-type cross-sectional views for explaining an example of planarization using the conventional bias sputtering method, and Figure 2 shows an opening in a silicon oxide film with a diameter of 2.5 μm and a depth of 1 μm. Schematic cross section at the opening when molybdenum is deposited on a substrate with a target side power density of 5.7 W/cm ² and a bias voltage of -600 V under sputtering conditions with an argon gas pressure of 3 mTorr and an interelectrode distance of 95 mm. Figures 3a to 3c are schematic cross-sectional views for explaining one embodiment of the method of the present invention. 101, 201, 301...Silicon substrate, 1
02,302...Insulating film such as silicon oxide film, 2
02...Silicon oxide film, 103...Opening part, 1
04, 303, 304... Conductive film such as molybdenum film, 203... Molybdenum film, 204... Groove formed along the bottom of the step.

Claims (1)

[Claims] 1. A step covering method in which the insulating film pattern is filled with a conductive film using a bias sputtering method on a substrate having an insulating film pattern formed on the surface, which does not cause microcracks in the deposited conductive film. A first step of embedding the pattern up to a part of the height of the pattern under sputtering conditions that does not create a groove along the bottom of the pattern step in the base substrate, and filling the unfilled portion of the pattern with an adhered conductor film. There are no microcracks, and the thickness of the conductive film on the flat surface between the patterns is approximately equal to the sum of the height of the step in the pattern and the thickness of the conductive film on the flat surface above the step of the pattern. A method for covering a step, the method comprising: a second step of embedding under sputtering conditions.