JPS60233840A - Coating method for stepwise difference - Google Patents

Abstract

PURPOSE:To obtain a flat conductive film over the aperture of a steep side surface by a method wherein the ratio of the coating speed of a conductor film adhered to the flat Si substrate surface in the aperture of an insulation film, to the coating speed of said film to the flat surface on a stepwise difference is controlled by adjustment of coating conditions of substrate bias voltage and so on. CONSTITUTION:A flat Su substrate 201 is coated with a CVDSiO2 film 202, and an apeture (h) is formed. When an Al film 203 is ion-plated by biasing the substrate at about -5kV, neither micro cracks in the aperture nor grooves along the step bottom in the substrate 201 generates. Next, an Al film 205 is formed by biasing the substrate at about -30kV with the result that the Al coating speed on the flat surface 204 in the aperture is about twice that on the flat surface on the hole, step, when an almost flat Al film can be obtained. This manner enables film coating and flattening at the same time in fine apertures in the same vacuum system by using ion plating and can prevent wiring step cuts.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for covering steps, and in particular to a method for forming a multilayer thin film structure or a method for covering surfaces with steep steps such as the side surfaces of minute openings. The present invention relates to a method for forming a conductive film.

[Prior art and its problems]

For example, wiring in a semiconductor device is performed by depositing a conductive film on a base insulating film having minute openings. At this time, according to the conventional sputtering method or vapor deposition method, the wiring tends to be cut or thinned at the shoulder part of the step of the opening, and the manufacturing yield and reliability of LSI are significantly lowered.

In order to prevent these drawbacks, the side surfaces of minute openings are tapered and sloped so that the conductive film can be coated uniformly. Providing slopes on the side surfaces hinders high integration of LSIs, and is not a desirable method for improving L2. Therefore, methods have been proposed for depositing a conductive film with good step coverage on steep and deep steps, and one of them is
One method is the aluminum vacuum port ■ method. It was reported by Mr. M. J. Cooke et al. that a film with good step coverage can be formed by depositing an aluminum film using the reduced pressure Q0 method.
State Technology) Volume 25, No. 12
No. 62-65. However, in a multilayer wiring structure, even if a film formation method with good step coverage is used, there is a drawback that the dimensional processing accuracy of the upper layer pattern deteriorates as each step accumulates.

When depositing a conductor film onto the fine openings in a multilayer thin film structure such as LSI6 or VLSI wiring, one important thing is to prevent micro-cracks from forming the fine openings into the deposited film. One is to fill the fine openings without causing them, and the other is to make the surface flat after a conductive film is deposited to fill the minute openings.

In particular, these two factors are extremely important in order to achieve high integration and multi-layering of LSIs and to obtain high reliability. However, when trying to realize the multilayer thin film structure as described above using conventional sputtering or vapor deposition methods, the process of filling the opening and planarizing the conductor film are separated into a large number of processes, and a large number of equipment are required. It had to be something complicated. A method using a lift-off method has been proposed as one method for flatly embedding between such patterns. The lift-off method using a resist is performed as shown in FIGS. 1(α) to (g). First, in Fig. 1 (→, 101 is a silicon substrate, 102 is a silicon oxide film formed on the silicon substrate 101, and after coating and patterning a resist 103 on the upper surface, the normal The silicon oxide film (insulating film) 102 is vertically etched by dry etching to form an opening.

Next, as shown in FIG. 1(c), a conductive film 10 is formed on the substrate.
4 is deposited. Thereafter, as shown in FIG.
As shown in Figure (e), a conductive film 105 is deposited on the substrate 101 to a required thickness to cover the silicon oxide film 102. In such a lift-off method, it is necessary to fill the openings of the insulating film 104 with the conductive film 104 without causing microcracks in the deposited film, and to prevent the conductive film 104 from adhering to the sides of the resist as much as possible in order to remove the resist. Therefore, the method or conditions for depositing the conductive film 104 are important.Usually, conventional vapor deposition methods or sputtering methods are used to fill the openings in the insulating film 102 with the conductive film 104 without microcracks. In this case, either the film was deposited under conditions that provided good step coverage, or the film was deposited using a vapor deposition method that provided good film deposition directionality. However, when using a deposition method with good deposition directionality, such as electron beam evaporation, the film is deposited in a cross-sectional shape as shown in FIG. Cannot be embedded. Furthermore, when using a vapor deposition method or a sputtering method under deposition conditions that provide good step coverage, the side surfaces of the resist are covered with a conductive film as shown in FIG. 3, making it impossible to dissolve the resist and prevent slope-off. In this way, flat filling between patterns using the lift-off method involves many separate steps of filling the opening and flattening the conductor film, and is technically difficult.

[Purpose of the invention]

SUMMARY OF THE INVENTION The purpose of the present invention is to solve the problems of the conventional method of covering steps, and to provide a method for covering steps that flatly fills minute openings with a conductive film without causing microcracks in the adhered conductor film. It is about providing.

[Structure of the invention]

The present invention provides a process for embedding an insulating film pattern with a conductive film on a substrate having an insulating film pattern formed on its surface using an ion blating method, without causing microcracks in the adhered conductive film. A first step of embedding the pattern up to a part of the height of the pattern under film deposition conditions that do not cause grooves along the bottom of the pattern step on the base substrate, and depositing the portion of the pattern that has not been filled yet. The thickness of the conductive film on the flat surface between the patterns is approximately equal to the sum of the height of the step of the pattern and the thickness of the conductive film on the flat surface above the step of the pattern without causing microcracks in the conductor film. This is a step covering method characterized by performing a second step of embedding under equal film deposition conditions.

[Principle of the invention]

In the present invention, a large substrate bias voltage (several tens of kilovolts), which has not been used in conventional DC or high frequency ion blating methods, is applied to the substrate.

Figures 4 (CL) to (C) show that when a film is deposited on a substrate with fine openings using the ion blating method, the substrate bias voltage is OlV, vz(v) (however, 0 ＜■□〈v2) It is a schematic cross-sectional view at the opening part in the tonal case. As shown in FIG. 4 (α), when the substrate bias voltage is zero, the deposited film 103 does not have the same shape as the deposited film of the normal vapor deposition method, and the deposited film 103 has poor step coverage. Microcracks were generated. As the substrate bias voltage is applied, microcracks no longer occur in the deposited film inside the opening, as shown in FIG. In this case, an inclined surface 105 unique to the ion blating method is formed. Furthermore, Figure 4 (
As shown in C), when the substrate bias voltage exceeds a certain level, the thickness of the film deposited on the flat surface inside the opening becomes thicker than the thickness of the film deposited on the step of the opening. This phenomenon is thought to be due to the fact that the sputter-etched film deposited on the side surfaces inside the opening re-adheres to the flat surface inside the opening. Therefore, the ratio between the thickness of the film 103 deposited on the flat surface 106 inside the aperture and the thickness of the film deposited on the flat surface 106 above the step of the aperture is determined by adjusting the substrate bias voltage or other film coating. By appropriately adjusting the wearing conditions, it is possible to increase the amount by more than 1 times. However, in the case of FIG. 4(5), a groove 10 is formed along the bottom of the step near the opening in the substrate.
6 occurred. Therefore, at the initial stage of film deposition, the grooves 106
It is necessary to use substrate bias voltage conditions that do not cause this.

〔Example〕

Examples of the present invention will be described below. Figure 5 (α)
-(C) are schematic cross-sectional views showing one embodiment step by step. FIG. 5(α) shows a state in which a silicon oxide film 102 is deposited on a silicon substrate 201 with a flat surface by the G method, and then an opening is formed through the usual photoresist process and dry etching process. show. Next, as shown in FIG. 5(b), aluminum adheres to the inside of the opening without forming microcranks, and the base silicon substrate 201 is coated with aluminum.
In this case, when the substrate bias voltage was increased after the aluminum film 203 was deposited by ion blating under substrate bias conditions in which no groove was formed along the bottom of the step near the opening, the step of the insulating film on the underlying silicon substrate 201 was removed. Apply only a thickness that does not create grooves along the bottom of the base. The substrate bias voltage at this time was about 5 KV. Next, Figure 5 (C
), the film deposition speed of the aluminum film deposited on the flat surface 204 inside the opening is about 2 times the deposition speed of the aluminum film deposited on the flat surface 204 on the step of the opening. An aluminum film 205 is deposited on the flat surface on the step of the opening by ion blating under twice the substrate bias condition. Under this condition, the thickness of the aluminum film inside the opening is twice the thickness of the aluminum film on the flat surface 2 ( ) 4 on the step of the opening, and the thickness of the aluminum film inside the opening is twice that of the aluminum film on the flat surface 2 ( ) 4 on the step of the opening. The aluminum film becomes almost flat. The substrate bias voltage at this time was about 30 KV.

〔Effect of the invention〕

As explained above, the present invention improves the ratio of the film deposition speed of the conductor film onto the flat surface of the opening and the film deposition speed of the conductor film onto the flat surface above the step of the opening. (This is done using the ion blating method, which can be increased by more than 1 time by adjusting the Iasumi pressure or other film deposition conditions. As a result, the film is applied to the minute openings using the ion brating method. When performing deposition, film deposition and planarization can be performed simultaneously in the same vacuum system, and a conductive film can be formed flat over an opening in an insulating film that has steep sides.

In addition, if applied to the formation of multilayer thin film structures, it is possible to avoid step breakage, poor contact, and deterioration of dimensional processing accuracy in higher-order thin films that will be formed later, and when used in LSIs, reliability and integration can be dramatically improved. can be improved.

In the embodiment, an aluminum film is deposited, but there is no need to be limited to this; other metals such as molybdenum, and alloys such as polycrystalline silicon doped with impurities and silicide can also be used.

[Brief explanation of drawings]

Figures 1 (α) to (g) are schematic cross-sectional views illustrating the formation of a flat conductor film using a resist or the foot-off method. Fig. 3 is a schematic cross-sectional view of a structure in which a pattern is embedded with a conductive film using a vapor deposition method with good step coverage, and Fig. 4 (α) to (1) are ion blating Figures 5 (α) to (C) are schematic cross-sectional views at the opening when the substrate bias voltage is used as a parameter in film deposition on a substrate with fine openings using the method. FIG. 1 is a schematic cross-sectional view for explaining one embodiment of the method of the invention. 201...Silicon substrate, 202...Insulating film such as silicon oxide film, 203...Conductor film Patent applicant NEC Corporation Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Procedural amendment (voluntary ) 1. Indication of the incident 1982 Patent Application No. 089678
No. 2, Title of the invention: Method for attaching a step 3, Relationship with the case of the person making the amendment Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent 5. "Detailed Description of the Invention" column of the specification to be amended. 6. Contents of the amendment (1) rVl, V2 J on page 7, line 8 of the specification will be corrected to r-Vl, -V2 J. (2) On page 9, line 8 of the specification, [about 5KVJ] is corrected to about 1 -5KVJ. (3) The statement "about 30KVJ" on page 9, line 19 of the specification is corrected to "about -3QKVJ. ~ Attorney Patent Attorney Uchihara Sai

Claims (1)

[Claims] (1) In the step of embedding the insulating film pattern with a conductive film using the ion blating method on a substrate with an insulating film pattern formed on the surface, the process does not cause microcracks in the adhered conductive film and the substrate A first step of embedding the previous pattern up to a part of the height of the pattern under film deposition conditions that do not create a groove along the bottom of the pattern step on the substrate, and for a portion of the pattern that is not yet filled, The thickness of the adhered conductor film on the flat surface between the patterns is the same as the height of the step of the butter 7 and the thickness of the adhered conductor film on the flat surface above the step of the pattern without causing a 1-cycle crack in the adhered conductor film. and a second step of embedding this portion under film deposition conditions such that /mi is equal to the sum of .