JPH01173957U - - Google Patents
Info
- Publication number
- JPH01173957U JPH01173957U JP1988069057U JP6905788U JPH01173957U JP H01173957 U JPH01173957 U JP H01173957U JP 1988069057 U JP1988069057 U JP 1988069057U JP 6905788 U JP6905788 U JP 6905788U JP H01173957 U JPH01173957 U JP H01173957U
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- lsi chip
- substrate
- bump
- prevention part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002265 prevention Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の構成を示す断面図
、第２図は従来の構成を示す断面図である。
符号の説明、１：ＬＳＩチツプ、２：バンプ、
３：インナーリード、４：フレキシブル基板、６
：短絡防止部。
FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, and FIG. 2 is a sectional view showing the conventional structure. Explanation of symbols, 1: LSI chip, 2: bump,
3: Inner lead, 4: Flexible board, 6
: Short circuit prevention part.
Claims (1)
ードを有するフイルムキヤリア用フレキシブル基
板に於いて、上記インナーリードとＬＳＩチツプ
・エツジ部の接触を防止する短絡防止部を設けた
ことを特徴とするフイルムキヤリア用フレキシブ
ル基板。 A flexible substrate for a film carrier having an inner lead connected to a bump of an LSI chip, characterized in that a short-circuit prevention part is provided to prevent contact between the inner lead and the edge of the LSI chip. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988069057U JPH01173957U (en) | 1988-05-25 | 1988-05-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988069057U JPH01173957U (en) | 1988-05-25 | 1988-05-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01173957U true JPH01173957U (en) | 1989-12-11 |
Family
ID=31294351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988069057U Pending JPH01173957U (en) | 1988-05-25 | 1988-05-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01173957U (en) |
-
1988
- 1988-05-25 JP JP1988069057U patent/JPH01173957U/ja active Pending
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