JPS6169863U - - Google Patents

Info

Publication number
JPS6169863U
JPS6169863U JP1984153365U JP15336584U JPS6169863U JP S6169863 U JPS6169863 U JP S6169863U JP 1984153365 U JP1984153365 U JP 1984153365U JP 15336584 U JP15336584 U JP 15336584U JP S6169863 U JPS6169863 U JP S6169863U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
matches
substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984153365U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984153365U priority Critical patent/JPS6169863U/ja
Publication of JPS6169863U publication Critical patent/JPS6169863U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案一実施例による集積回路装置を
示す断面図、第２図は従来のプリント配線基板を
用いた集積回路装置を示す断面図である。 １……プリント回路基板（基材）、２……銅箔
配線、３……ソルダーレジスト、４……フリツプ
チツプ、５……銅箔配線端子、６……フリツプチ
ツプのバンプ、７……感光性フイルムレジスト、
８……開口部、９……樹脂枠、１０……封止樹脂
。 FIG. 1 is a sectional view showing an integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing an integrated circuit device using a conventional printed wiring board. 1... Printed circuit board (base material), 2... Copper foil wiring, 3... Solder resist, 4... Flip chip, 5... Copper foil wiring terminal, 6... Bump of flip chip, 7... Photosensitive film resist,
8...Opening portion, 9...Resin frame, 10...Sealing resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 搭載される半導体素子との接合部の寸法に合つ
た開口を有する絶縁層が基板上に設けられている
ことを特徴とする集積回路装置。 An integrated circuit device characterized in that an insulating layer is provided on a substrate and has an opening that matches the size of a bonding portion with a semiconductor element to be mounted.
JP1984153365U 1984-10-11 1984-10-11 Pending JPS6169863U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984153365U JPS6169863U (en) 1984-10-11 1984-10-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984153365U JPS6169863U (en) 1984-10-11 1984-10-11

Publications (1)

Publication Number Publication Date
JPS6169863U true JPS6169863U (en) 1986-05-13

Family

ID=30711399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984153365U Pending JPS6169863U (en) 1984-10-11 1984-10-11

Country Status (1)

Country Link
JP (1) JPS6169863U (en)

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