JPS6387889U - - Google Patents
Info
- Publication number
- JPS6387889U JPS6387889U JP18305086U JP18305086U JPS6387889U JP S6387889 U JPS6387889 U JP S6387889U JP 18305086 U JP18305086 U JP 18305086U JP 18305086 U JP18305086 U JP 18305086U JP S6387889 U JPS6387889 U JP S6387889U
- Authority
- JP
- Japan
- Prior art keywords
- electronic device
- integrated circuit
- semiconductor integrated
- flat package
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の一実施例を示す断面図、第２
図はフラツトパツケージタイプの半導体集積回路
装置を示す断面図、第３図は従来のプリント回路
基板による実装方法を示す断面図である。
１１，１２……フラツトパツケージタイプの半
導体集積回路装置、１３，１４……樹脂モールド
層、１５，１６……外部リード、１７……プリン
ト回路基板、１８……放熱板、１９……半田、２
０……プリント配線、２１……プリント回路基板
の上面と下面のプリント配線をつなぐためスルー
ホール部、１……樹脂モールド層、２……外部リ
ード、３……プリント回路基板、４……半田、５
……プリント配線。
Fig. 1 is a sectional view showing one embodiment of the present invention;
The figure is a sectional view showing a flat package type semiconductor integrated circuit device, and FIG. 3 is a sectional view showing a conventional mounting method using a printed circuit board. 11, 12... Flat package type semiconductor integrated circuit device, 13, 14... Resin mold layer, 15, 16... External lead, 17... Printed circuit board, 18... Heat sink, 19... Solder, 2
0...Printed wiring, 21...Through hole for connecting the printed wiring on the top and bottom surfaces of the printed circuit board, 1...Resin mold layer, 2...External lead, 3...Printed circuit board, 4...Solder ,5
...Printed wiring.
Claims (1)
ージタイプの半導体集積回路装置とリードを下方
に折り曲げたフラツトパツケージタイプの半導体
集積回路装置とが放熱板をはさんで取り付けられ
、前記放熱板には絶縁体を介して導電配線層が形
成されていることを特徴とする電子装置。 (2) 前記実用新案登録請求の範囲第１項におい
て、通常のフラツトパツケージに実装された半導
体集積回路装置を２個用いて、一方を背面実装す
ることを特徴とする電子装置。[Scope of Claim for Utility Model Registration] (1) A flat package type semiconductor integrated circuit device with leads bent upward and a flat package type semiconductor integrated circuit device with leads bent downward with a heat sink sandwiched between them. 1. An electronic device, wherein the electronic device is attached to an electronic device, and a conductive wiring layer is formed on the heat sink via an insulator. (2) The electronic device according to claim 1 of the utility model registration, characterized in that two semiconductor integrated circuit devices are mounted on a normal flat package, one of which is back-mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18305086U JPS6387889U (en) | 1986-11-27 | 1986-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18305086U JPS6387889U (en) | 1986-11-27 | 1986-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6387889U true JPS6387889U (en) | 1988-06-08 |
Family
ID=31129425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18305086U Pending JPS6387889U (en) | 1986-11-27 | 1986-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6387889U (en) |
-
1986
- 1986-11-27 JP JP18305086U patent/JPS6387889U/ja active Pending
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