JPH0115100B2 - - Google Patents

Info

Publication number
JPH0115100B2
JPH0115100B2 JP57183475A JP18347582A JPH0115100B2 JP H0115100 B2 JPH0115100 B2 JP H0115100B2 JP 57183475 A JP57183475 A JP 57183475A JP 18347582 A JP18347582 A JP 18347582A JP H0115100 B2 JPH0115100 B2 JP H0115100B2
Authority
JP
Japan
Prior art keywords
data
transmitting
receiving
buffer
queue buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57183475A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5972539A (ja
Inventor
Kenichi Yukimatsu
Hiroshi Fujitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57183475A priority Critical patent/JPS5972539A/ja
Publication of JPS5972539A publication Critical patent/JPS5972539A/ja
Publication of JPH0115100B2 publication Critical patent/JPH0115100B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
JP57183475A 1982-10-18 1982-10-18 デ−タ転送方式 Granted JPS5972539A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57183475A JPS5972539A (ja) 1982-10-18 1982-10-18 デ−タ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57183475A JPS5972539A (ja) 1982-10-18 1982-10-18 デ−タ転送方式

Publications (2)

Publication Number Publication Date
JPS5972539A JPS5972539A (ja) 1984-04-24
JPH0115100B2 true JPH0115100B2 (de) 1989-03-15

Family

ID=16136441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57183475A Granted JPS5972539A (ja) 1982-10-18 1982-10-18 デ−タ転送方式

Country Status (1)

Country Link
JP (1) JPS5972539A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62120761A (ja) * 1985-11-20 1987-06-02 Fujitsu Ltd デ−タ送受信制御方式
DE3689151D1 (de) * 1986-12-30 1993-11-11 Ibm Nicht-sperrender Warteschlangenmechanismus.
WO1989007296A1 (en) * 1988-01-27 1989-08-10 Storage Technology Corporation An early start mode method and apparatus

Also Published As

Publication number Publication date
JPS5972539A (ja) 1984-04-24

Similar Documents

Publication Publication Date Title
US4419728A (en) Channel interface circuit providing virtual channel number translation and direct memory access
CA1227879A (en) Buffer system for input/output portion of digital data processing system
US4521850A (en) Instruction buffer associated with a cache memory unit
EP0239937A2 (de) Serielle Übertragungssteuerungsvorrichtung
JPH0115100B2 (de)
US5432910A (en) Coupling apparatus and method for increasing the connection capability of a communication system
JPH0744567B2 (ja) 通信インタ−フエイス装置
JP2859178B2 (ja) プロセッサ間データ転送方式及びプロセッサ間データ転送用リングバッファメモリ
KR950009763B1 (ko) 2개의 cpu로 구성된 시스팀에서의 cpu간 데이타 전송 및 동기화 방법
US7051148B2 (en) Data transmission sequencing method associated with briding device and application system
US6345332B1 (en) Bus interchange apparatus and dual system for accessing a fault information register without regard to buffer conditions
EP0789363B1 (de) Speichersystem und Datenkommunikationssystem
JPH087738B2 (ja) エンディアン変換方式
JP2505298B2 (ja) スプリットバスにおける可変バス幅指定方式及び可変バス幅情報受信方式
US5799158A (en) adapter for transferring blocks of data having a variable size to other adapters via a main system bus
JP2576236B2 (ja) プログラマブルコントローラの通信方法
JPH0476148B2 (de)
JPS5920130B2 (ja) 過剰デ−タ転送制限方式
JPH04163664A (ja) 分散メモリ型の並列計算機システム
JPS6143366A (ja) デ−タ転送方式
JPH0120774B2 (de)
JPS6240558A (ja) 通信処理装置
JPH0525215B2 (de)
JPH0459820B2 (de)
JPH0652516B2 (ja) バス・インターフェース装置