DE3689151D1 - Nicht-sperrender Warteschlangenmechanismus. - Google Patents

Nicht-sperrender Warteschlangenmechanismus.

Info

Publication number
DE3689151D1
DE3689151D1 DE86430058T DE3689151T DE3689151D1 DE 3689151 D1 DE3689151 D1 DE 3689151D1 DE 86430058 T DE86430058 T DE 86430058T DE 3689151 T DE3689151 T DE 3689151T DE 3689151 D1 DE3689151 D1 DE 3689151D1
Authority
DE
Germany
Prior art keywords
queue mechanism
locking queue
locking
queue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE86430058T
Other languages
English (en)
Inventor
Didier Francis Villa Le Giroir
Alvin Paul Mullery
Andre Pauporte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3689151D1 publication Critical patent/DE3689151D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/123—Contention resolution, i.e. resolving conflicts between simultaneous read and write operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE86430058T 1986-12-30 1986-12-30 Nicht-sperrender Warteschlangenmechanismus. Expired - Lifetime DE3689151D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86430058A EP0273083B1 (de) 1986-12-30 1986-12-30 Nicht-sperrender Warteschlangenmechanismus

Publications (1)

Publication Number Publication Date
DE3689151D1 true DE3689151D1 (de) 1993-11-11

Family

ID=8196418

Family Applications (1)

Application Number Title Priority Date Filing Date
DE86430058T Expired - Lifetime DE3689151D1 (de) 1986-12-30 1986-12-30 Nicht-sperrender Warteschlangenmechanismus.

Country Status (4)

Country Link
US (1) US4980852A (de)
EP (1) EP0273083B1 (de)
JP (1) JPS63168732A (de)
DE (1) DE3689151D1 (de)

Families Citing this family (35)

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Publication number Priority date Publication date Assignee Title
EP0418447B1 (de) * 1989-09-20 1995-01-18 International Business Machines Corporation Vorrichtung zur Nachrichtenwarteschlangenbetriebssteuerung in einem Speicher
US5239634A (en) * 1989-09-21 1993-08-24 Digital Equipment Corporation Memory controller for enqueuing/dequeuing process
GB8921653D0 (en) * 1989-09-26 1989-11-08 Lucas Ind Plc Interface circuit
JPH0619759B2 (ja) * 1990-05-21 1994-03-16 富士ゼロックス株式会社 マルチプロセッサシステムにおける相互通信方法
US5224215A (en) * 1990-07-13 1993-06-29 International Business Machines Corporation Message queue processing among cooperative processors having significant speed differences
JP2836283B2 (ja) * 1991-04-11 1998-12-14 日本電気株式会社 バッファ管理方式
FR2676845B1 (fr) * 1991-05-23 1993-09-24 Sextant Avionique Dispositif pour la gestion de plusieurs files d'attente independantes dans un espace memoire commun et banalise.
CA2125607A1 (en) * 1993-06-30 1994-12-31 David Thielen Method and system for buffering transient data
US5581705A (en) * 1993-12-13 1996-12-03 Cray Research, Inc. Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system
US5548728A (en) * 1994-11-04 1996-08-20 Canon Information Systems, Inc. System for reducing bus contention using counter of outstanding acknowledgement in sending processor and issuing of acknowledgement signal by receiving processor to indicate available space in shared memory
US5696991A (en) * 1994-11-29 1997-12-09 Winbond Electronics Corporation Method and device for parallel accessing data with optimal reading start
US6446224B1 (en) * 1995-03-03 2002-09-03 Fujitsu Limited Method and apparatus for prioritizing and handling errors in a computer system
US5649157A (en) * 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
US5841973A (en) * 1996-03-13 1998-11-24 Cray Research, Inc. Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory
US5864738A (en) * 1996-03-13 1999-01-26 Cray Research, Inc. Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
US5938747A (en) * 1997-03-13 1999-08-17 Adapter, Inc. Hardware command block delivery queue for host adapters and other devices with onboard processors
US6012107A (en) * 1997-05-22 2000-01-04 Adaptec, Inc. Hardware control block delivery queues for host adapters and other devices with onboard processors
US6115761A (en) * 1997-05-30 2000-09-05 Lsi Logic Corporation First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment
US6615296B2 (en) 1997-05-30 2003-09-02 Lsi Logic Corporation Efficient implementation of first-in-first-out memories for multi-processor systems
IL125271A0 (en) * 1998-07-08 1999-03-12 Galileo Technology Ltd Head of line blocking
US6216174B1 (en) 1998-09-29 2001-04-10 Silicon Graphics, Inc. System and method for fast barrier synchronization
US6449614B1 (en) 1999-03-25 2002-09-10 International Business Machines Corporation Interface system and method for asynchronously updating a share resource with locking facility
US6687729B1 (en) * 1999-12-20 2004-02-03 Unisys Corporation System and method for providing a pool of reusable threads for performing queued items of work
GB2382898B (en) 2000-12-29 2005-06-29 Zarlink Semiconductor Ltd A method of managing data
GB0031761D0 (en) * 2000-12-29 2001-02-07 Mitel Semiconductor Ltd Data queues
JP2005509943A (ja) * 2001-11-13 2005-04-14 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ セマフォを使用する効率的なｆｉｆｏ通信
TW573254B (en) * 2002-01-07 2004-01-21 Via Tech Inc Message transmission queue and operation method thereof
CN100437466C (zh) * 2002-06-07 2008-11-26 Nxp股份有限公司 向/从fifo存储器读取/写入数据单元的设备和方法
JP4765485B2 (ja) * 2005-08-26 2011-09-07 ソニー株式会社 情報処理装置、情報記録媒体、および情報処理方法、並びにコンピュータ・プログラム
US8046837B2 (en) 2005-08-26 2011-10-25 Sony Corporation Information processing device, information recording medium, information processing method, and computer program
US9448856B2 (en) * 2005-12-30 2016-09-20 Level 3 Communications, Llc Lock-free dual queue with condition synchronization and time-outs
US7904789B1 (en) * 2006-03-31 2011-03-08 Guillermo Rozas Techniques for detecting and correcting errors in a memory device
JP4905587B2 (ja) * 2010-12-28 2012-03-28 ソニー株式会社 情報処理装置、および情報処理方法、並びにコンピュータ・プログラム
US9196347B2 (en) * 2013-03-14 2015-11-24 International Business Machines Corporation DRAM controller for variable refresh operation timing
US10409800B2 (en) * 2015-08-03 2019-09-10 Sap Se Priority queue for exclusive locks

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL165859C (nl) * 1975-04-25 1981-05-15 Philips Nv Station voor informatie-overdracht.
JPS51135337A (en) * 1975-05-19 1976-11-24 Mitsubishi Electric Corp Data treatment device
DE2714106C3 (de) * 1977-03-30 1982-01-14 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Verfahren zum Zwischenspeichern von Informationen in einem FIFO-Speicher
US4402046A (en) * 1978-12-21 1983-08-30 Intel Corporation Interprocessor communication system
DE3149678C2 (de) * 1981-12-15 1984-02-23 Siemens AG, 1000 Berlin und 8000 München Anordnung zur Zwischenspeicherung von zwischen zwei Funktionseinheiten in beiden Richtungen zu übertragenden Informationen in einem Pufferspeicher
US4507760A (en) * 1982-08-13 1985-03-26 At&T Bell Laboratories First-in, first-out (FIFO) memory configuration for queue storage
JPS5972539A (ja) * 1982-10-18 1984-04-24 Nippon Telegr & Teleph Corp <Ntt> デ−タ転送方式
NL8501143A (nl) * 1985-04-19 1986-11-17 Philips Nv Kommunikatiesysteem voorzien van een eerst-in-eerst-uit-buffer.
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4783730A (en) * 1986-09-19 1988-11-08 Datapoint Corporation Input/output control technique utilizing multilevel memory structure for processor and I/O communication

Also Published As

Publication number Publication date
EP0273083A1 (de) 1988-07-06
US4980852A (en) 1990-12-25
EP0273083B1 (de) 1993-10-06
JPS63168732A (ja) 1988-07-12

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Legal Events

Date Code Title Description
8332 No legal effect for de