JPH01118935A - Measurement system for program comprehension rate - Google Patents

Abstract

PURPOSE:To accurately grasp the degree of evaluation of a program to be evaluated by applying a system where the rate is measured for the instructions carried out at least once or more during evaluation of said program. CONSTITUTION:A system consists of an input device 1 which performs the input operations, a program comprehension rate measuring device 2, a CPU 3, a main memory 4, and an output device 5. The executed instruction area information is successively stored in the executing processes of programs 41-4n to be evaluated by means of a branch instruction interruption. Then the ratio of the executed instructions of the programs 41-4n is calculated based on the stored executed instruction area information after execution of the programs 41-4n. Thus it is possible to measure the ratio of the number of executed instructions as a program comprehension rate with no work applied to the programs 41-4n. As a result, the degrees of evaluation of the programs 41-4n can be accurately grasped.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for measuring program coverage in a computer system, and in particular, when one or more programs to be evaluated with different priority levels are executed, the method is executed at least once or more. This invention relates to a method of measuring the ratio of executed instructions to the total number of instructions for each evaluation target program.

[Conventional technology]

When a new program is developed, the program is evaluated using test data or the like in order to confirm whether the program achieves its intended purpose.

Normally, in evaluating this program, the person in charge of evaluation considers several evaluation items in advance to cover all instructions in the program to be evaluated, conducts tests on these evaluation items, and finds results that are satisfactory in all evaluation items. When this was obtained, the evaluation was considered complete.

[Problem that the invention seeks to solve]

However, it is extremely difficult to think of evaluation items in advance that can cover all the instructions in the program to be evaluated, and therefore it is considered that the evaluation of the program to be evaluated is complete when all the evaluation items that have been considered in advance are satisfied. The problem was that it was impossible to say.

The present invention has been made in view of these circumstances,
The purpose of this is to provide a method for measuring the ratio of instructions executed at least once during the evaluation of a program to be evaluated, thereby making it possible to accurately determine the degree of evaluation of the program to be evaluated. .

[Means for solving problems]

In order to achieve the above object, the present invention responds to the setting of a branch instruction interrupt mode that includes the specification of a priority level when running a program, and executes a branch instruction in the program with the specified priority level, so that In a computer system having a branch instruction interrupt mechanism that holds the priority level, pre-branch address, and post-branch address and generates an internal interrupt before the first instruction is executed,
post-branch address storage means for storing post-branch addresses in correspondence with the priority levels; executed instruction area information storage means; and when an internal interrupt is generated by the branch instruction interrupt mechanism, information stored in the branch instruction interrupt mechanism is provided. The range indicated by the pre-branch address and the post-branch address stored in the post-branch address storage means corresponding to the priority level held in the branch instruction interrupt mechanism is used as executed instruction area information. Coverage rate measurement control means for storing in the instruction area information storage means and storing the post-branch address held in the branch instruction interrupt mechanism in the post-branch address storage means in correspondence with the priority level; instruction word analysis means for obtaining addresses of all instruction words of the evaluation target program; addresses of all instruction words of the evaluation target program obtained by the instruction word analysis means; and execution information stored in the executed instruction area information storage means. Based on the completed instruction area information, the ratio of executed instructions in the designated evaluation target program is calculated as a program running time rate and outputted from the output device, and the executed instructions and unexecuted instructions can be distinguished. and measurement result editing output control means for outputting the address of the command word from the output device.

[Effect]

When a branch instruction in an evaluation target program that has a pre-specified priority level during program execution is executed, the branch instruction interrupt mechanism retains the priority level, pre-branch address, and post-branch address, and generates an internal interrupt. be done.

When this internal interrupt occurs,! The i1m rate measurement control means includes a pre-branch address held in the branch instruction interrupt mechanism;
The range indicated by the previous post-branch address stored in the post-branch address storage means corresponding to the current priority level is stored as executed instruction area information in the executed instruction area information storage means, and the branch instruction allocation The post-branch address currently held by the loading mechanism is stored in post-branch address storage means in correspondence with the priority level. Such processing is
It is executed every time a branch instruction in the evaluation target program of the specified priority level is executed, and as a result, when the evaluation target program finishes execution, information indicating the area of the executed instruction among the areas of the evaluation target program is executed. It will be stored in the completed instruction area information storage means. Thereafter, the measurement result editing output control means performs evaluation based on the addresses of all instructions of the evaluation target program obtained from the instruction word analysis means and the executed instruction area information stored in the executed instruction area information storage means. The ratio of executed instructions in the target program is calculated and output as the program coverage rate, and
The address of the instruction word is output so that executed instructions and unexecuted instructions can be distinguished.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the program coverage measurement method of the present invention. , a central processing unit 3 , a main storage device 4 , and an output device 5 .

In the central processing unit 3, in response to a branch instruction interrupt mode setting including a priority level specification, the first instruction after the branch is executed by executing the branch instruction in the program of the specified priority level. A branch instruction interrupt mechanism 30 is provided in front of the branch instruction interrupt mechanism 30 that holds the priority level, pre-branch address, and post-branch address and generates an internal interrupt. Also,
The program 'fi4 ratio measurement device 2 includes an input information analysis section 20, a coverage measurement control section 21, a post-branch address storage section 22 that can store post-branch addresses for each priority level,
An executed instruction area information storage section 23, a measurement result editing output control section 24, an instruction word analysis section 25, and a 'fi4 ratio calculation section 26.

The main storage device 4 contains a plurality of evaluation target programs 41, 4.
2. ..., 4n exist, and the start address of each is 31. S2. ..., Sn address, and the same (end address is El, E2..., En address).

And evaluation target program 41.42. ..., 4
The priority levels of n when running are (II, (21
,...,(n).

Next, the operation of the program coverage measurement method of this embodiment configured as described above will be explained.

In the present invention, the program coverage rates of a plurality of programs to be evaluated that exist in the main storage device 4 can be measured individually, and it is also possible to simultaneously measure the program coverage rates of a plurality of programs to be evaluated that have different priority levels. You can also do it. Now, there are two programs to be evaluated: 41 and 42! 114
If the i rate is measured at the same time, from the input device 1 via the input information analysis section 20 of the program coverage measurement device 2,
(1) which is the priority level of the evaluation target program 41 and (2) which is the priority level of the evaluation target program 42,
The coverage rate measurement control unit 21 is notified.

Upon receiving this notification, the coverage measurement control unit 21 sets the priority level to +11. (21 is set to the branch instruction interrupt mode and the branch instruction interrupt mechanism 30 is activated, and the priority level is (1).

The post-branch address in the post-branch address storage unit 22 corresponding to (2) is initialized to zero. After this, the evaluation target programs 41 and 42 in the main storage device 4 are started.

When a branch instruction is executed during execution of the evaluation target program 41 or 42, the branch instruction interrupt mechanism 30 of the central processing unit 3 interrupts the running priority level ((1) when executing the branch instruction of the evaluation target program 41). , +2)) 1 post-branch address when executing a branch instruction in the evaluation target program 42.

The pre-branch address is held and a branch instruction interrupt is generated at the branch destination address, and w4 of the program coverage measurement device 2
The vehicle side control section 21 is operated.

The vehicle side measurement control unit 21 generates a branch instruction interrupt by using the priority level held in the branch instruction interrupt mechanism 30, the pre-branch address which is the address of the branch instruction itself, and the post-branch address which is the branch destination of this branch instruction. The range from the post-branch address corresponding to the priority level received from the branch address storage unit 22 to the pre-branch address received this time is stored as executed instruction area information in the executed instruction area information storage unit 23. At the same time, the branch address storage unit 2 corresponding to the currently received priority level stores the currently received post-branch address.
Store it in a location within 2. In addition, w4 vehicle side constant control section 21
is the post-branch address storage unit 2 corresponding to the priority level number.
At the time of the first branch instruction interrupt in which the post-branch address in 2 is initialized to zero, the post-branch address notified from the branch instruction allocation mechanism 30 is stored in the post-branch address storage unit 22 in correspondence with the current priority level. After performing 0 or more operations that only store the executed instruction area information and do not store the executed instruction area information in the executed instruction area information storage unit 23, 1iI
The fI rate measurement control unit 21 instructs the branch instruction interrupt mechanism 30 to resume execution from the post-branch address in the evaluation target program 41 or 42, and waits for the next branch instruction interrupt.

FIG. 2 is a diagram illustrating the operation of this embodiment when storing executed instruction area information in the executed instruction area information storage unit 23, taking the routine from address PO to address P4 of the evaluation target program 41 as an example. be. In the evaluation target program 41, addresses PO, PI, P2. P3. P
4 is the branch destination address (post-branch address) of the branch instruction, and addresses B1, B2 . B3. B4 is the address of the branch instruction itself (pre-branch address). First, when a branch instruction that branches to address PO of the evaluation target program 41 is executed, a branch instruction interrupt is generated by the branch instruction interrupt mechanism 30, and yi The vehicle side control section 21 operates. The coverage measurement control unit 21 stores the post-branch address PO notified from the branch instruction interrupt mechanism 30 in the post-branch address storage unit 22 in correspondence with the priority level 11) (here, the address PO before branching to the address PO is stored in the post-branch address storage unit 22). (The explanation of the procedure for storing executed instruction area information is omitted.)

Next, when a branch instruction at address B1 of the evaluation target program 41 is executed and a branch instruction interrupt occurs at address P1, which is the branch destination, the y4N rate measurement control unit 21 receives a branch instruction from the branch instruction interrupt mechanism 30. Previous address Bl and
At this time, the priority level (1) is set in the post-branch address storage unit 22.
The range with the address PO stored in correspondence is stored in the executed instruction area information storage unit 23 as executed instruction area information M1, and then the post-branch address PI notified together with the pre-branch address B1 is stored in the post-branch address storage unit. 22 priority level + 1 + stored in the corresponding position. Similarly, address B
2. By executing branch instructions B3 and B4, addresses P2. P3. A branch instruction interrupt occurs at P4, mm
The m measurement control unit 21 generates executed command area information M2. M3. M4 is stored in the executed instruction area information storage section 23.

FIG. 3 is a diagram showing an example of the stored contents of the executed instruction area information storage section 23. As shown in FIG. The executed instruction area information storage unit 23 of this embodiment has a focus that corresponds one-to-one with each address in the main memory. For example, a bit with bit number 0 is stored in address O in the main memory, The bit corresponds to address 100 on main memory.

Then, the bit of the bit number corresponding to the address of the executable instruction is turned on, and the bit corresponding to the address of the unexecuted instruction is turned off.For example, taking the evaluation target program 41 as an example, Since the start address on the main memory is address 81 and the end address is address E1, the executed instruction area information of the evaluation target program 41 is
is stored in the storage area 23-1 in the range from bit number S1 to bit number El in the executed instruction area information storage unit 230. The executed instruction area information storage area 23-1 includes a second
Executed instruction area information Ml, M2 . M3゜M
4 exists and executed instruction area information Ml, M2°M3.
All bits contained in M4 are on.

Similarly, bits corresponding to other executed instruction areas of the evaluation target program 41 in the executed instruction area information storage area 23-1 are also stored in the executed instruction area information M1, M2. M
3. Like M4, it is on, and the other bits, that is, the bits corresponding to unexecuted instruction areas of the evaluation target program 41, are off.

Now, in Figure 1, the program to be evaluated is 41°42
After completion of execution, when a branch instruction interrupt mode release command of priority level (1), (2+) is notified from the input device l to the coverage measurement control unit 21 via the input information analysis unit 20, v
4. The vehicle side control unit 21 sets the priority level +11. +21
Release the branch instruction interrupt mode of the branch instruction interrupt mechanism 3.
0, and first instructs the measurement result editing output control unit 24 to edit and output the measurement results for the evaluation target program 41 of priority level (1).

Upon receiving this instruction, the measurement result editing output control section 24 instructs the instruction word analysis section 25 to report the addresses of all instruction words from address 81 to address E1. In response, the instruction word analysis section 25 interprets all the instruction words from address 81 to address E1 and sequentially reports the addresses of all instruction words to the measurement result editing output control section 24.

When the instruction word address is reported from the instruction word analysis section 25, the measurement result editing output control section 24, based on the reported address and the state of the bit in the executed instruction area information storage section 23, Only addresses whose bits are off, that is, addresses of unexecuted instructions, are output to the output device 5. Furthermore,
The measurement result editing output control section 24 counts the number of instruction words sequentially reported by the instruction word analysis section 25, and
The number of times the bit in the executed instruction area information storage area 23-1 corresponding to the address of the reported instruction word is on is counted, that is, the number of execution method instructions, and finally the execution method instruction is The coverage calculation unit 26 is caused to calculate the ratio of the number of words to the total number of command words.

The coverage calculation unit 26 calculates the result of dividing the number of execution method command words by the total number of command words, for example, in the form of a percentage based on the above-mentioned count value, and notifies the measurement result editing output control unit 24 . The measurement result editing output control unit 24 outputs this calculation result to the output device 5 as a program coverage rate for the evaluation target program 41.

Then, the completion of the w4 ratio measurement at priority level (1) is reported to the y4 ratio vehicle side constant control unit 21.

Upon receiving this report, the kilometer vehicle side setting control unit 21 instructs the measurement result editing output control unit 2 to edit and output the measurement results for the evaluation target program 42 of priority level (2).
4. As a result, the same processing as described above is performed, and the addresses of unexecuted instructions of the evaluation target program 42 and the program coverage rate are output from the output device 5. FIG. 4 shows an example of the measurement results output from the output device 5 in this manner.

〔Effect of the invention〕

As explained above, the present invention uses branch instruction interrupts to sequentially store executed instruction area information during the execution process of the evaluation target program, and after the execution of the evaluation target program is finished, the executed instruction area information is stored in the stored executed instruction area. Based on the information, the ratio of executed instructions of the program to be evaluated is calculated, without any modification to the program to be evaluated.
The ratio of the number of execution method instructions can be measured as the program coverage rate. Therefore, it is possible to accurately grasp the evaluation level of the program to be evaluated.

In addition to outputting the ratio of the number of execution method instructions of the program to be evaluated, it is also possible to identify which instructions in the program to be evaluated by outputting the address of the instruction word so that executed instructions and unexecuted instructions can be distinguished. It becomes easy to determine whether a command is an unexecuted instruction, and in the next evaluation step, evaluation can be performed focusing on unexecuted instructions, and the degree of evaluation of the program can be efficiently improved.

Furthermore, since the post-branch address is stored in the post-branch address storage means in correspondence with the priority level, and the execution method instruction area is determined for each priority level, the coverage rate of multiple evaluation target programs with different priority levels can be measured simultaneously. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation when storing executed instruction area information in the executed instruction area information storage section 23, and FIG. 3 is an executed instruction area information storage FIG. 4 is a diagram showing an example of the contents of the note tρ in the section 23, and FIG. 4 is a diagram showing an example of the output of the measurement results. In the figure, 1... Input device 2... Program y4 Rate measuring device 3... Central processing unit 4... Main storage device 5... Output device 20... Input information analysis section 21...・Coverage rate measurement control unit 22...Post-branch address storage unit 23...Executed instruction area information storage unit 24...Measurement result editing output control unit 25...Instruction word analysis unit 26...Coverage rate Calculation unit 30...branch instruction interrupt mechanism 41-4n...program to be evaluated

Claims (1)

[Claims] In response to the setting of a branch instruction interrupt mode that includes the specification of a priority level during program execution, the first instruction after the branch is executed by executing a branch instruction in the program with the specified priority level. In a computer system having a branch instruction interrupt mechanism that holds the priority level, pre-branch address, and post-branch address and generates an internal interrupt before the branch is executed, the branch stores the post-branch address in correspondence with the priority level. a post-address storage means; an executed instruction area information storage means; a pre-branch address held in the branch instruction interrupt mechanism when an internal interrupt occurs by the branch instruction interrupt mechanism; and a pre-branch address held in the branch instruction interrupt mechanism; The range indicated by the post-branch address stored in the post-branch address storage means corresponding to the priority level set is stored as executed instruction area information in the executed instruction area information storage means, and the branch instruction interrupt coverage measurement control means for storing post-branch addresses held in the mechanism in the post-branch address storage means in correspondence with the priority level; and instruction word analysis means for obtaining addresses of all instruction words of a designated program to be evaluated. and a specified evaluation target program based on the addresses of all instruction words of the evaluation target program obtained by the instruction word analysis means and the executed instruction area information stored in the executed instruction area information storage means. Measurement result editing output control that calculates the ratio of executed instructions in as a program coverage rate and outputs it from the output device, and outputs the address of the instruction word from the output device so that executed instructions and unexecuted instructions can be distinguished. A program coverage measurement method characterized by comprising: means.