JPS63300335A - Measurement system for number of times of instruction execution of program - Google Patents

Measurement system for number of times of instruction execution of program

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Publication number
JPS63300335A
JPS63300335A JP62133382A JP13338287A JPS63300335A JP S63300335 A JPS63300335 A JP S63300335A JP 62133382 A JP62133382 A JP 62133382A JP 13338287 A JP13338287 A JP 13338287A JP S63300335 A JPS63300335 A JP S63300335A
Authority
JP
Japan
Prior art keywords
instruction
branch
address
interrupt
priority level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62133382A
Other languages
Japanese (ja)
Inventor
Kenichi Murakami
健一 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62133382A priority Critical patent/JPS63300335A/en
Publication of JPS63300335A publication Critical patent/JPS63300335A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain reference for the performance improvement of a program (specially, a control program) by outputting execution times by priority levels to a measurement result list to be edited and outputted. CONSTITUTION:A measurement result editing and output part 23 calculates the execution time of a priority level 1 (multiplies the number of times of execution in an instruction execution frequency storage array 61 by an execution time in an instruction execution time correspondence table 7 and totalizes multiplication results by the instructions), and edits and outputs the calculation result to an output device 8. The execution time of even the same instruction in the instruction execution time correspondence table 7 is different, so the execution times of the instructions are made to correspond by the kinds of the instructions and the kinds of computers, thereby measuring the execution time of each priority level by the kinds of the computers.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、情報処理システムに於けるプログラムの性能
測定方式に関し、特にプログラムの命令実行数を測定し
実行時間を算出する方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring the performance of a program in an information processing system, and particularly to a method for measuring the number of executed instructions of a program and calculating the execution time.

臥下糸自 〔従来の技術〕 従来、プログラムの性能の基準となるプログラムの命令
実行数を知るには、机上でプログラムの実行過程を予測
しながら命令実行数を計算するか。
[Prior art] Conventionally, in order to find out the number of instructions executed in a program, which is the standard of program performance, it is necessary to calculate the number of instructions executed while predicting the program execution process on a desk.

またはハード、ウェアモニタにより命令実行数を測定す
る方法が取られている。
Another method is to measure the number of executed instructions using a hardware or software monitor.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のように、机上でプログラムの実行過程を予測しな
がらit実行数を計算する場合には、プログラムの内容
を良く理解していなければならず。
As mentioned above, when calculating the number of IT executions while predicting the program execution process on a desk, the contents of the program must be well understood.

また、プログラムの内容を良く理解した担当者であって
も相当の時間を必要とする。一方ハードウェアモニタに
より命令実行数を測定する方法では。
Furthermore, even for a person in charge who has a good understanding of the contents of the program, a considerable amount of time is required. On the other hand, there is a method that measures the number of executed instructions using a hardware monitor.

測定の準備が面倒なため、一般にソフトウェア担当者は
使用していないのが現状である。
Currently, software engineers generally do not use it because it is troublesome to prepare for measurement.

本発明の目的はプログラムの内容を理解することなく、
容易に命令実行数を測定することのできる命令実行数測
定方式を提供することにある。
The purpose of the present invention is to
An object of the present invention is to provide a method for measuring the number of executed instructions that can easily measure the number of executed instructions.

〔問題点を解決するための手段〕 本発明によるプログラムの命令実行数測定方式ば1分岐
命令の実行により分岐後最初の命令が実行される前に優
先レベルと分岐前アドレスと分岐後アドレスとを保持し
て内部割込み全発生させ且つこの内部割込みが一個以上
の優先レベル毎に発生できるような分岐命令割込み手段
と、この分岐命令割込み手段の起動および停止を行なう
ための分岐命令割込みモード設定解除手段と、優先レベ
ルに対応させて分岐後アドレスを記憶する分岐後アドレ
ス記憶手段と1分岐命令割込み時に分岐命令割込み手段
から通知される分岐前アドレスと分岐後アドレス記憶手
段によりこの分岐命令割込みの一度前の分岐命令割込み
時に記憶されていてこの分岐命令割込み時の優先レベル
に対応する分岐後アドレスとで示される範囲に存在する
命令を探索し命令の種類毎の個数を解析する命令解析手
段と、この命令解析手段による解析結果である命令の種
類毎の個数を命令の種類毎に且つ優先レベル毎に対応さ
せて累積し記憶する命令数記憶手段と命令毎の実行時間
を示す命令実行時間対応情報を備え、命令数記憶手段に
より累積記憶された命令の種類毎の個数と命令実行時間
対応情報とをもとに優先レベル毎の実行時間を算出する
とともに編集出力する測定結果編集出力手段とを有する
ことを特徴としている。
[Means for Solving the Problems] The method for measuring the number of executed instructions in a program according to the present invention measures the priority level, pre-branch address, and post-branch address before the first instruction after the branch is executed by executing one branch instruction. A branch instruction interrupt means that can hold and generate all internal interrupts and generate this internal interrupt for each priority level of one or more, and a branch instruction interrupt mode setting canceling means for starting and stopping this branch instruction interrupt means. and a post-branch address storage means that stores post-branch addresses in correspondence with priority levels, and a pre-branch address and post-branch address storage means that are notified from the branch instruction interrupt means at the time of a 1-branch instruction interrupt. an instruction analysis means for searching for instructions existing in a range indicated by a post-branch address stored at the time of a branch instruction interrupt and corresponding to a priority level at the time of the branch instruction interrupt, and analyzing the number of each type of instruction; A number storage means for accumulating and storing the number of each type of instruction, which is an analysis result by the instruction analysis means, corresponding to each type of instruction and each priority level, and instruction execution time correspondence information indicating the execution time of each instruction. and measurement result editing/output means for calculating the execution time for each priority level based on the number of each type of instructions cumulatively stored by the instruction number storage means and instruction execution time correspondence information, and editing and outputting the same. It is characterized by

〔実施例〕〔Example〕

次に9本発明について実施例により説明する。 Next, nine aspects of the present invention will be explained using examples.

第1図は2本発明によるプログラムの命令実行数測定方
式の一実施例の構成を示すブロック図である。第1図を
参照して、プログラムの命令実行数測定方式は1人力操
作が行なわれる入力装置1と、入力情報解析部20と制
御部21と命令語解析部22と測定結果編集出力部23
とを含むプログラム命令実行数測定装置2と9分岐命令
の実行により分岐後最初の命令が実行される前に優先レ
ベルと分岐前アドレスと分岐後アドレスとを保持して内
部割込みを発生させる分岐命令割込機構30を含む中央
処理装置3と、測定対象プログラム41.42・・・e
4n’に含む主記憶装置4と、優先レベル毎に対応する
分岐後アトVス51,52゜−−−、5n f次の分岐
命令割込み時まで記憶しておく分岐後アドレス記憶部5
と、命令毎の実行回数を優先レベル毎に対応して記憶す
る命令実行数記憶部6と、命令毎の実行時間を示す命令
実行時間対応表7と、測定結果リストが出力される出力
装置8とを備えている・ 命令実行数記憶部6は、命令の区別を示す命令列60と
、優先レベル毎に対応し且つ命令列60の命令毎に対応
しその命令の実行回数を記憶する 。
FIG. 1 is a block diagram showing the configuration of an embodiment of a method for measuring the number of executed instructions of a program according to the present invention. Referring to FIG. 1, the method for measuring the number of executed instructions of a program includes an input device 1 that is manually operated, an input information analysis section 20, a control section 21, a command word analysis section 22, and a measurement result editing/output section 23.
a program instruction execution count measurement device 2 including a program instruction execution count measuring device 2; and 9 a branch instruction that holds a priority level, a pre-branch address, and a post-branch address and generates an internal interrupt before the first instruction after the branch is executed by executing the branch instruction; The central processing unit 3 including the interrupt mechanism 30 and the measurement target programs 41, 42...e
4n', and a post-branch address storage unit 5 that stores the post-branch addresses corresponding to each priority level until the interrupt of the next branch instruction.
, an instruction execution number storage unit 6 that stores the number of executions of each instruction corresponding to each priority level, an instruction execution time correspondence table 7 that shows the execution time of each instruction, and an output device 8 that outputs a measurement result list. The instruction execution number storage unit 6 stores an instruction string 60 indicating the distinction of instructions, and the number of executions of the instruction corresponding to each priority level and for each instruction in the instruction string 60.

命令実行回数記憶列61,62.・・・、6n(それぞ
れ優先レベル1,2.・・・nに対応)とを含んでいる
。また、命令実行時間対応表7は、命令の区別を示す命
令列70と、命令列70の命令毎に対応しその命令の実
行時間を示す命令実行時間列71とを含んでいる。
Instruction execution count storage columns 61, 62 . . . , 6n (corresponding to priority levels 1, 2, . . . n, respectively). Further, the instruction execution time correspondence table 7 includes an instruction sequence 70 indicating the distinction between instructions, and an instruction execution time sequence 71 corresponding to each instruction in the instruction sequence 70 and indicating the execution time of that instruction.

ここで9本実施例では、測定対象プログラム41が優先
レベル1で動作し、且つ分岐後アドレス51と命令実行
回数記憶列61とが慶先Vベル1に対応する。と仮定し
て説明する。同様に、測定対象プログラム42は優先ン
ベル2で動作し2分岐後アドレス52と命令実行回数記
憶列62とが優先レベル2に対応する。従って、測定対
象プログラム4nは優先レベルnで動作し9分岐後アド
レス5nと命令実行回数記憶列6nとが優先レベルnに
対応する。
In this embodiment, the measurement target program 41 operates at priority level 1, and the post-branch address 51 and the instruction execution number storage column 61 correspond to the destination Vbell 1. The explanation will be based on the assumption that Similarly, the measurement target program 42 operates at priority level 2, and the post-2-branch address 52 and instruction execution number storage column 62 correspond to priority level 2. Therefore, the measurement target program 4n operates at the priority level n, and the address 5n after 9 branches and the instruction execution number storage column 6n correspond to the priority level n.

次に、上述のプログラムの命令実行数測定方式の動作に
ついて説明する。まず、測定対象プログラム41を測定
する場合、測定対象プログラム41の優先レベル番号1
が入力装置1から入力される。入力情報解析部20は、
この入力された優先レベル番号1を制御部21に通知す
る。この通知を受けた制御部21は、優先レベル番号1
を分岐命令割込みモードにして9分岐命令割込機構30
ft起動すると共に、優先レベル番号1に対応する命令
実行数記憶部6内の命令実行回数記憶列61と分岐後ア
ドレス記憶部5内の分岐後アドレス51とをゼロで初期
化する。その後、主記憶装置4内での測定対象プログラ
ム41が起動されて分岐命令が実行されると、中央処理
装置3の分岐命令割込機構30は分岐先のアドレスで分
岐命令割込みを発生させてプログラム命令実行数測定装
置2の制御部211c動作させる。制御部21は。
Next, the operation of the method for measuring the number of program instruction executions described above will be explained. First, when measuring the measurement target program 41, the priority level number 1 of the measurement target program 41 is
is input from the input device 1. The input information analysis unit 20
The input priority level number 1 is notified to the control unit 21. Upon receiving this notification, the control unit 21 selects priority level number 1.
9 branch instruction interrupt mechanism 30 in branch instruction interrupt mode.
ft is activated, and the instruction execution number storage column 61 in the instruction execution number storage unit 6 corresponding to priority level number 1 and the post-branch address 51 in the post-branch address storage unit 5 are initialized to zero. Thereafter, when the measurement target program 41 in the main storage device 4 is started and a branch instruction is executed, the branch instruction interrupt mechanism 30 of the central processing unit 3 generates a branch instruction interrupt at the branch destination address to program the program. The control unit 211c of the instruction execution count measuring device 2 is operated. The control section 21 is.

分岐命令割込機構30によって優先レベル番号1と測定
対象プログラム41内の分岐命令自身のアドレスである
分岐前アドレスとこの分岐命令による分岐先である分岐
後アドレスとが通知されると。
When the branch instruction interrupt mechanism 30 notifies the priority level number 1, the pre-branch address which is the address of the branch instruction itself in the measurement target program 41, and the post-branch address which is the branch destination of this branch instruction.

分岐後アドレス記憶部5内の優先レベル番号1に対応す
る分岐後アドレス51の内容が示すアドレス(測定対象
プログラム41内のアドレス)からこの分岐命令割込み
時通知された分岐前アドレスまでの範囲内にある命令を
解析するよう命令語解析部22に指示すると共に、この
分岐命令割込み時通知された分岐後アドレスが優先レベ
ル番号1に対する次の分岐命令割込み時まで分岐後アド
レス51に記憶される。命令語解析部22は、制御部2
1によって指示された範囲内の命令を解析し。
Within the range from the address indicated by the content of the post-branch address 51 corresponding to priority level number 1 in the post-branch address storage unit 5 (address in the measurement target program 41) to the pre-branch address notified at the time of this branch instruction interrupt. The instruction word analysis unit 22 is instructed to analyze a certain instruction, and the post-branch address notified at the time of this branch instruction interrupt is stored in the post-branch address 51 until the next branch instruction interrupt for priority level number 1. The instruction word analysis unit 22 is a control unit 2
Analyze instructions within the range indicated by 1.

この解析結果(命令の種類毎の数)を優先レベル番号I
K対応する命令実行回数記憶列61内の命令の種類に対
応させて加算する。なお、制御部21は9分岐後アドレ
ス51がゼロで初期化されている最初の分岐命令割込み
時には9分岐命令割込機構30から通知された分岐後ア
ドレスを分岐後アドレス51に記憶するだけで、命令語
解析部22に対して命令の解析指示をしない。以上の動
作を行なった後、制御部21は測定対象プログラム41
での分岐後アドレスからの実行再開を分岐命令割込機構
30に指示し9次の分岐命令割込み待ちとなる。
This analysis result (number of each type of instruction) is assigned the priority level number I.
K is added in correspondence with the type of instruction in the corresponding instruction execution count storage column 61. Note that the control unit 21 only stores the post-branch address notified from the 9-branch instruction interrupt mechanism 30 in the post-branch address 51 at the time of the first branch instruction interrupt when the post-9 branch address 51 is initialized with zero. Does not instruct the instruction word analysis unit 22 to analyze the instruction. After performing the above operations, the control unit 21 controls the measurement target program 41.
It instructs the branch instruction interrupt mechanism 30 to resume execution from the address after the branch at , and waits for the ninth branch instruction interrupt.

ここで、プログラム命令実行数測定装置2の命令語解析
部22が解析する範囲について測定対象プログラム41
のアドレスPOからアドレスP4までのルーチンを例と
して説明する。
Here, the range to be analyzed by the instruction word analysis unit 22 of the program instruction execution count measuring device 2 is determined by the measurement target program 41.
The routine from address PO to address P4 will be explained as an example.

第2図も参照して、測定対象プログラム41に於いて、
アドレスPO,PL、P2.P3.P4は分岐命令の分
岐先アドレスであり、アドレスB1.B2.B3tB4
は分岐命令自身のアドレスである。まず、測定対象プロ
グラム41のアドレスpoに分岐する分岐命令(図示せ
ず)が実行されると9分岐命令割込機構30によって分
岐命令割込みが発生し、プログラム命令実行数測定装置
2(の制御部21)が動作する。プログラム命令実行数
測定装置2(の制御部21)は分岐命令割込機構30か
ら通知されるアドレスPOを分岐後アドレス51に記憶
する(ここではアドレスpoに分岐する前の範囲に対す
る動作手頴の説明を省略する)。次に測定対象プログラ
ム41のアドレスBlでの分岐命令が実行され9分岐先
であるアドレスP1で分岐命令割込みが発生し、プログ
ラム命令実行数測定装置2(の命令語解析部22)は分
岐命令割込機構30から通知されるアドレスB1とこの
とき分岐後アドレス51が記憶しているアドレスPOと
の範囲(アドレスPOからアドレスB1まで)にある命
令を解析して、解析結果(命令の種類毎の数)を命令実
行回数記憶列61内の命令の種類に対応させて加算する
Referring also to FIG. 2, in the measurement target program 41,
Addresses PO, PL, P2. P3. P4 is the branch destination address of the branch instruction, and address B1. B2. B3tB4
is the address of the branch instruction itself. First, when a branch instruction (not shown) that branches to address po of the measurement target program 41 is executed, a branch instruction interrupt is generated by the 9 branch instruction interrupt mechanism 30, and the control unit 21) works. The program instruction execution count measuring device 2 (control unit 21) stores the address PO notified from the branch instruction interrupt mechanism 30 in the post-branch address 51 (here, the operation handbook for the range before branching to the address po) (Description omitted). Next, the branch instruction at address Bl of the measurement target program 41 is executed and a branch instruction interrupt occurs at address P1, which is the 9th branch destination, and the program instruction execution number measuring device 2 (instruction word analysis unit 22) detects the branch instruction interrupt. The instructions in the range (from address PO to address B1) between the address B1 notified from the loading mechanism 30 and the address PO stored in the post-branch address 51 at this time are analyzed, and the analysis results (for each type of instruction) are analyzed. ) is added in correspondence with the type of instruction in the instruction execution count storage column 61.

この後、プログラム命令実行数測定装置2(の制御部2
1)は、アドレスB1と共に通知されたアドレスP1t
−分岐後アドレス51に記憶する。
After this, the control unit 2 of the program instruction execution count measuring device 2
1) is the address P1t notified together with the address B1.
- Store in post-branch address 51.

同様に、アドレスB2tB3.n4の分岐命令の実行に
よってそれぞれアドレスP2.P3.P4で分岐命令割
込みが発生し、このときグログラム命令実行数測定装置
2(の命令語解析部22)によって解析されるのは、そ
れぞれ、アドレスP1からアドレスB2までの範囲と、
アドレスP2から7)’L’スB3Jでの範囲と、アド
レスP3から7ドvy、f34までの範囲である。なお
2分岐命令割込み時に分岐命令割込機構30から通知さ
れるのは9分岐命令自身のアドレス(B1.B2゜B3
.B4)と分岐命令の分岐先アドレス(POlPI、P
2.P3.P4)の他に、測定対象プログラム41の優
先レベル番号(図示せず)もあり。
Similarly, address B2tB3. By executing the branch instruction of n4, each address P2. P3. A branch instruction interrupt occurs at P4, and at this time, the programmatic instruction execution count measuring device 2 (instruction word analysis unit 22) analyzes the range from address P1 to address B2, and
The range is from address P2 to 7) 'L' space B3J, and the range from address P3 to 7th dovy, f34. Note that when a 2-branch instruction interrupts, the address of the 9-branch instruction itself (B1.B2°B3) is notified from the branch instruction interrupt mechanism 30.
.. B4) and the branch destination address of the branch instruction (POlPI, P
2. P3. P4), there is also a priority level number (not shown) of the program to be measured 41.

この優先レベル番号によって分岐後アドレス51と命令
実行回数記憶列61とが選択可能となる。
The post-branch address 51 and instruction execution count storage column 61 can be selected based on this priority level number.

測定対象グログラム41に対する測定が終了し。The measurement of the measurement target grogram 41 is completed.

優先レベル番号1の分岐命令割込みモード解除指令が入
力装置lから入力される。入力情報解析部20は、この
入力された優先レベル番号1に対する分岐命令割込みモ
ード解除指令を制御部21に通知する。この通知を受け
た制御部21は、優先レベル番号1の分岐命令割込みモ
ードを解除して。
A branch instruction interrupt mode release command with priority level number 1 is input from the input device l. The input information analysis unit 20 notifies the control unit 21 of the branch instruction interrupt mode release command for the input priority level number 1. Upon receiving this notification, the control unit 21 cancels the branch instruction interrupt mode of priority level number 1.

分岐命令割込機構30を停止する(分岐命令割込みモー
ド中の優先レベルが他にあれば停止しない)と共に、優
先レベル番号1に対する測定結果を編集出力するように
測定結果編集出力部23に指示する。この指示を受けた
測定結果編集出力部23は、命令実行回数記憶列61と
命令実行時間対応表7とをもとに、優先レベルlの実行
時間を算出しく命令の種類毎に対応して、命令実行回数
記憶列61内の実行回数と命令実行時間対応表7内の実
行時間とを乗算し、命令毎の乗算結果を合計する)、こ
の算出結果を出力装置8に編集出力する。
The branch instruction interrupt mechanism 30 is stopped (it will not be stopped if there is another priority level in the branch instruction interrupt mode), and the measurement result editing/output unit 23 is instructed to edit and output the measurement results for priority level number 1. . Upon receiving this instruction, the measurement result editing output unit 23 calculates the execution time of priority level l based on the instruction execution count storage column 61 and the instruction execution time correspondence table 7, and calculates the execution time for each type of instruction. The number of executions in the instruction execution number storage column 61 is multiplied by the execution time in the instruction execution time correspondence table 7, and the multiplication results for each instruction are summed), and this calculation result is edited and output to the output device 8.

なお1分岐後アドレス記憶部5内の分岐後アドレスと、
命令実行数記憶部6内の命令毎に実行回数を記憶する命
令実行回数記憶列とは、優先レベル毎に存在し記憶でき
るため2以上述べた優先レベルlで走行する測定対象プ
ログラム41単独の測定だけでなく、複数の優先レベル
(測定対象プログラム42.・・・、4n)を同時に測
定することが可能である。更に、命令実行時間対応表7
で示される命令の実行時間は、同じ命令であっても計算
機の種類によって異なるため、命令の種類毎に且つ計算
機の種類毎に命令の実行時間を対応させるように構成し
、計算機の種類毎に優先レベル毎の実行時間を測定する
ことが可能となる。
Note that the post-branch address in the post-branch address storage unit 5,
The instruction execution number storage column that stores the number of executions for each instruction in the instruction execution number storage unit 6 exists and can be stored for each priority level. In addition, it is possible to simultaneously measure a plurality of priority levels (programs to be measured 42, . . . , 4n). Furthermore, instruction execution time correspondence table 7
The execution time of an instruction shown by is different depending on the type of computer even if it is the same instruction. It becomes possible to measure the execution time for each priority level.

i下色臼 〔発明の効果〕 以上説明したように本発明では2分岐命令割込みを利用
してプログラムの命令実行数を測定するため、プログラ
ムの内容を全く知らなくとも命令実行数測定することが
でき、測定のための手続きも簡単であり、さらに測定の
ための時間も机上で計算場合に比較して大幅に減少する
。また9編集出力される測定結果リストには、優先レベ
ル毎に実行時間が算出され出力されるため、プログラム
(特に制御プログラム)の性能を改善する場合には、大
変参考になる。
i Lower color mill [Effect of the invention] As explained above, in the present invention, the number of executed instructions of a program is measured using the two-branch instruction interrupt, so it is possible to measure the number of executed instructions without knowing the contents of the program at all. The measurement procedure is simple, and the time required for measurement is significantly reduced compared to when calculations are performed on a desk. In addition, since the execution time is calculated and output for each priority level in the measurement result list that is edited and output, it is very useful when improving the performance of a program (especially a control program).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図。 第2図はプログラム命令実行数測定装置の命令語解析部
が解析する範囲を具体的に説明するための関連図である
。 図において。 1・・・入力装置、2・・・プログラム命令実行数測定
装置、3・・・中央処理装置、4・・・主記憶装置、5
・・・分岐後アドレス記憶部、6・・・命令実行数記憶
部。 7・・・命令実行時間対応表、 8−・・出方装置、で
ある。
FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a related diagram for specifically explaining the range analyzed by the instruction word analysis section of the program instruction execution count measuring device. In fig. DESCRIPTION OF SYMBOLS 1... Input device, 2... Program instruction execution number measuring device, 3... Central processing unit, 4... Main storage device, 5
. . . Post-branch address storage unit, 6 . . . Instruction execution number storage unit. 7--Instruction execution time correspondence table, 8---Output device.

Claims (1)

【特許請求の範囲】[Claims] 1、分岐命令の実行により分岐後最初の命令が実行され
る前に当該分岐命令を含むプログラムの走行の優先レベ
ルと分岐命令自身のアドレスである分岐前アドレスと分
岐命令の分岐先アドレスである分岐後アドレスとを保持
して内部割込みを発生させ且つ該内部割込みを一個以上
の前記優先レベル毎に発生する分岐命令割込み手段と、
該分岐命令割込み手段の起動および停止を行なうための
分岐命令割込みモード設定解除手段と、前記優先レベル
に対応させて前記分岐後アドレスを記憶する分岐後アド
レス記憶手段と、分岐命令割込み時に前記分岐命令割込
み手段から通知される前記分岐前アドレスと前記分岐後
アドレス記憶手段により当該分岐命令割込みの一度前の
分岐命令割込み時に記憶されていて当該分岐命令割込み
時の前記優先レベルに対応する前記分岐後アドレスとで
示される範囲に存在する命令を探索し命令の種類毎の個
数を解析する命令解析手段と、該命令解析手段による解
析結果である命令の種類毎の個数を命令の種類毎に且つ
前記優先レベル毎に対応させて累積し記憶する命令数記
憶手段と、命令毎の実行時間を示す命令実行時間対応情
報を備え、前記命令数記憶手段により累積記憶された命
令の種類毎の個数と前記命令実行時間対応情報とをもと
に前記優先レベル毎の実行時間を算出するとともに編集
出力する測定結果編集出力手段とを有することを特徴と
するプログラムの命令実行数測定方式。
1. Before the first instruction after a branch is executed by executing a branch instruction, the priority level of the program including the branch instruction, the pre-branch address which is the address of the branch instruction itself, and the branch address which is the branch destination address of the branch instruction. branch instruction interrupt means for generating an internal interrupt by holding a subsequent address and generating the internal interrupt for each of one or more of the priority levels;
branch instruction interrupt mode setting cancellation means for starting and stopping the branch instruction interrupt means; post-branch address storage means for storing the post-branch address in correspondence with the priority level; The pre-branch address notified from the interrupt means and the post-branch address that is stored by the post-branch address storage means at the time of a branch instruction interrupt immediately before the branch instruction interrupt and corresponds to the priority level at the time of the branch instruction interrupt. an instruction analysis means that searches for instructions existing in the range indicated by and analyzes the number of each type of instruction; and an instruction analysis means that searches for instructions existing in the range indicated by A number storage means for accumulating and storing instructions corresponding to each level, and instruction execution time correspondence information indicating an execution time for each instruction, the number of each type of instructions cumulatively stored by the number storage means and the instructions. A method for measuring the number of executed instructions of a program, comprising a measurement result editing/outputting means for calculating and editing an execution time for each priority level based on execution time correspondence information.
JP62133382A 1987-05-30 1987-05-30 Measurement system for number of times of instruction execution of program Pending JPS63300335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62133382A JPS63300335A (en) 1987-05-30 1987-05-30 Measurement system for number of times of instruction execution of program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62133382A JPS63300335A (en) 1987-05-30 1987-05-30 Measurement system for number of times of instruction execution of program

Publications (1)

Publication Number Publication Date
JPS63300335A true JPS63300335A (en) 1988-12-07

Family

ID=15103425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62133382A Pending JPS63300335A (en) 1987-05-30 1987-05-30 Measurement system for number of times of instruction execution of program

Country Status (1)

Country Link
JP (1) JPS63300335A (en)

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