JPH04241637A - System for measuring number of executed program instruction - Google Patents

System for measuring number of executed program instruction

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Publication number
JPH04241637A
JPH04241637A JP3002508A JP250891A JPH04241637A JP H04241637 A JPH04241637 A JP H04241637A JP 3002508 A JP3002508 A JP 3002508A JP 250891 A JP250891 A JP 250891A JP H04241637 A JPH04241637 A JP H04241637A
Authority
JP
Japan
Prior art keywords
branch
section
address
branch instruction
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3002508A
Other languages
Japanese (ja)
Inventor
Kenichi Murakami
健一 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3002508A priority Critical patent/JPH04241637A/en
Publication of JPH04241637A publication Critical patent/JPH04241637A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily and quickly measure the number of executed program instructions even when the content of the program is no known to the least. CONSTITUTION:An input device 1 performs inputting operations. A central processing unit 3 incorporates a branch instruction interrupting mechanism 30 which generates an internal interruption by holding a priority level, pre- branch address, and post-branch address before the first instruction is executed after branch by the execution of an branch instruction. A main storage device 4 stores a program 40 to be measured. A post-branch address storing section 5 stores post-branch addresses 51, 52,..., 5n corresponding to each priority level until the branch instruction is interrupted next. A section 6 for storing numbers of executed times by run sections stores numbers of instructions and numbers of executed times by run sections.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は情報処理システムにおけ
るプログラムの性能測定方式に関し、特に、プログラム
の命令実行数を測定するプログラム命令実行数測定方式
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring the performance of a program in an information processing system, and more particularly to a method for measuring the number of executed program instructions.

【0002】0002

【従来の技術】従来、プログラムの性能の基準となるプ
ログラムの命令実行数は、机上でプロの実行過程を予測
しながら計算するか、ハードウェアモニタにより測定す
る方法が取られていた。
2. Description of the Related Art Conventionally, the number of executed instructions of a program, which is a standard for program performance, has been calculated on a desk while predicting the execution process by a professional, or measured using a hardware monitor.

【0003】0003

【発明が解決しようとする課題】上記のように、机上で
プログラムの実行過程を予測しながら計算する場合には
、プログラムの内容を良く理解していなければならず、
また、プログラムの内容を良く理解した担当者であって
も担当の時間を必要とした。他の、ハードウェアモニタ
により測定する方法では、測定の準備が面倒なため、ソ
フトウェア担当者は一般に使用していないので現状であ
る。
[Problem to be Solved by the Invention] As mentioned above, when calculating on a desk while predicting the execution process of a program, it is necessary to have a good understanding of the contents of the program.
Furthermore, even those in charge who had a good understanding of the contents of the program required their own time. Other methods, such as measuring using a hardware monitor, require troublesome preparation for measurement, so software personnel generally do not use them at present.

【0004】0004

【課題を解決するための手段】本発明のプログラム命令
実行数測定方式は、分岐命令の実行により分岐後最初の
命令が実行される前に、当該分岐命令を含むプログラム
の走行の優先レベルと分岐命令自身のアドレスを示す分
岐前アドレスと分岐命令の分岐先アドレスを示す分岐後
アドレスとを保持して内部割込みを発生させかつ該内部
割込みが一個以上の前記優先レベルごとに発生できるよ
うな分岐命令割込み手段(30)と、該分岐命令割込み
手段の起動および停止を行なうための分岐命令割込みモ
ード設定・解除手段(21)と、前記優先レベルに対応
させて前記分岐後アドレスを記憶する分岐後アドレス記
臆手段(5)と、プログラム内を探索し分岐命令の位置
と当該分岐命令の分岐先アドレスに着目した走行区間を
設定(23)しつつ当該走行区間内の命令の個数を解析
する命令解析手段(22)と、分岐命令割込み毎に前記
分岐命令割込み手段から通知される分岐前アドレスと前
記分岐後アドレス記臆手段により当該分岐命令割込みの
一度前の分岐命令割込み時に記憶されていて当該分岐命
令割込み時の優先レベルに対応の分岐後アドレスとで示
される範囲に含まれる前記走行区間に対し実行回数を加
算する走行区間実行回数加算手段(24)と、前記命令
解析手段により設定された走行区間と当該走行区間内の
命令の個数に加え前記走行区間毎実行回数加算手段によ
り加算される走行区間毎の実行回数とを記憶する走行区
間毎実行回数記憶手段(6)と、前記走行区間毎実行回
数記憶手段により記憶された走行区間と走行区間毎命令
数と走行区間毎実行回数とを編集出力するとともに当該
記憶情報により走行区間毎命令実行数と当該走行区間毎
命令実行数が当該走行区間を含むプログラム全体に占め
る割合とを算出しつつ編集出力する測定結果編集出力手
段(25)とを具備することを特徴とする。
[Means for Solving the Problems] The method for measuring the number of executed program instructions of the present invention measures the execution priority level of the program including the branch instruction and the branch before the first instruction after the branch is executed. A branch instruction that generates an internal interrupt by holding a pre-branch address that indicates the address of the instruction itself and a post-branch address that indicates the branch destination address of the branch instruction, and that the internal interrupt can be generated for each of one or more of the priority levels. an interrupt means (30), a branch instruction interrupt mode setting/cancellation means (21) for starting and stopping the branch instruction interrupt means, and a post-branch address for storing the post-branch address in correspondence with the priority level. A recording means (5), and an instruction analysis that searches the program and sets a running section (23) focusing on the position of a branch instruction and the branch destination address of the branch instruction, and analyzes the number of instructions in the running section. means (22), and a pre-branch address notified from the branch instruction interrupt means every time a branch instruction interrupt occurs, and a post-branch address recording means that stores the pre-branch address and the post-branch address at the time of a branch instruction interrupt immediately before the branch instruction interrupt, A running section execution count adding means (24) that adds the number of executions to the running section included in the range indicated by the post-branch address corresponding to the priority level at the time of instruction interrupt; a number-of-execution-per-traveling section storage means (6) for storing a section and the number of instructions in the corresponding traveling section, as well as the number of executions per traveling section added by the number-of-executions-per-traveling adding means; The running section, the number of commands per running section, and the number of executions per running section stored by the execution number storage means are edited and outputted, and the number of commands executed per running section and the number of commands executed for each running section are calculated based on the stored information. The present invention is characterized by comprising measurement result editing/output means (25) that edits and outputs the measurement result while calculating the proportion of the entire program including the measurement result.

【0005】[0005]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

【0006】図1は本発明の一実施例の構成を示すブロ
ック図である。この図に示すプログラム命令実行数測定
方式は、入力操作が行なわれる入力装置1と、入力情報
解析部20と制御部21と命令語解析部22と走行区間
設定部23と実行回数加算部24と測定結果編集出力部
25とを含むプログラム命令実行数測定装置2と、分岐
命令の実行により分岐後最初の命令が実行される前に優
先レベルと分岐前アドレスと分岐後アドレスとを保持し
て内部割込みを発生させる分岐命令割込機構30を含む
中央処理装置3と、測定対象プログラム40を記憶する
主記憶装置4と、優先レベル毎に対応する分岐後アドレ
ス51,52,…,5nを次の分岐命令割込み時まで記
憶しておく分岐後アドレス記憶部5と、走行区間毎に命
令数と実行回数を記憶する走行区間毎実行回数記憶部6
と、測定結果リスト70が出力される出力装置7とを具
備する。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The method for measuring the number of executed program instructions shown in this figure includes an input device 1 on which input operations are performed, an input information analysis section 20, a control section 21, a command word analysis section 22, a running section setting section 23, and an execution number addition section 24. A program instruction execution count measuring device 2 including a measurement result editing output unit 25, and an internal memory that stores a priority level, a pre-branch address, and a post-branch address before the first instruction after a branch is executed by executing a branch instruction. The central processing unit 3 including the branch instruction interrupt mechanism 30 that generates an interrupt, the main storage device 4 that stores the measurement target program 40, and the post-branch addresses 51, 52, ..., 5n corresponding to each priority level are A post-branch address storage unit 5 that stores information until a branch instruction is interrupted; and an execution count storage unit 6 for each travel section that stores the number of instructions and the number of executions for each travel section.
and an output device 7 to which a measurement result list 70 is output.

【0007】主記憶装置4には、測定対象プログラム4
0が存在し、実行回数をP0、分岐命令自身のアドレス
をB1,B2,B3,B4,…として、これら分岐命令
による分岐先アドレスをP1,P2,P3,P4,…と
して表わしている。
The main storage device 4 stores a measurement target program 4.
0 exists, the number of executions is expressed as P0, the addresses of the branch instructions themselves are expressed as B1, B2, B3, B4, . . ., and the branch destination addresses of these branch instructions are expressed as P1, P2, P3, P4, .

【0008】走行区間毎実行回数記憶部6の内容は、測
定対象プログラム40の実行開始アドレスP0と分岐命
令の位置B1,B2,B3,B4,…と分岐先P1,P
2,P3,P4,…とによって区切られる走行区間列記
憶域60と、走行区間内での命令数を記憶する走行区間
内命令数記憶域61と、走行区間単位でみた実行回数が
累積記憶される走行区間毎実行回数列記憶域62とで構
成されている。
The contents of the execution count storage unit 6 for each running section include the execution start address P0 of the measurement target program 40, the positions B1, B2, B3, B4, etc. of branch instructions, and the branch destinations P1, P.
2, P3, P4, . . . , a running section column storage area 60 that stores the number of instructions within a running section, and a running section instruction number storage area 61 that stores the number of instructions executed in each running section. and a storage area 62 for a string of execution times for each running section.

【0009】次に、このように構成された本実施例のプ
ログラム命令実行数測定方式の動作について説明する。 最初に、測定対象プログラム40の走行区間設定指示が
入力装置1から入力される。入力情報解析部20は、入
力内容を解析した結果、測定対象プログラム40の走行
区間設定指示と解釈し制御部21に通知する。この通知
は、制御部21を通して命令語解析部22に入る。この
通知により命令語解析部22は、測定対象プログラム4
0の実行開始アドレスP0と分岐命令の位置B1,B2
,B3,B4,…と分岐先P1,P2,P3,P4,…
とによって区切られる走行区間P0〜B1,B1+1,
P1−1,P1〜B2−1,P2〜B2,B2+1〜B
3,B3+1〜P3−1,P3〜B4,B4+1〜P4
−1,…を解析設定し走行区間列記憶域60に記憶、同
時にこれら走行区間内での命令数も解析し走行区間内命
令数記憶域61に記憶する。さらに、走行区間毎実行回
数列記憶域62をゼロで初期化しておく。次に、測定対
象プログラム40の優先レベルが1と仮定した場合、優
先レベル番号1が入力装置1から入力される。入力情報
解析部20は、この入力された優先レベル番号1を制御
部21に通知する。この通知を受けた制御部21は、分
岐命令割込機構30に対して優先レベル番号1を分岐命
令割込みモードにして起動する。これと同時に、同じく
制御部21は分岐後アドレス記憶部5内の優先レベル番
号1に対応する分岐後アドレス51をゼロで初期化する
。この後、主記憶装置4上で測定対象プログラム40が
起動されて、測定対象プログラム40の分岐命令が実行
されると、中央処理装置3の分岐命令割込機構30は、
分岐命令で指定された分岐先のアドレスで分岐命令割り
込みを発生させて、この分岐命令割込みをプログラム命
令実行数測定装置2の制御部21に報告する。この報告
により制御部21は、優先レベル番号1と測定対象プロ
グラム40内の分岐命令割込みの原因となった分岐命令
自身のアドレスである分岐前アドレスと、この命令によ
る分岐先である分岐後アドレスとを知ることができる。 この報告された優先レベル番号1により制御部21は、
分岐後アドレス記憶部5内の優先レベル番号1に対応す
る分岐後アドレス51の内容を抽出することができ、実
行回数加算部24に対しこの抽出したアドレスとこの分
岐命令割込みでの分岐前アドレスとを通知するとともに
走行区間毎実行回数の加算を指示する。さらにこのとき
の分岐後アドレスは、次の分岐命令割込み時まで分岐後
アドレス51に記憶しておく。この後、実行回数加算部
24は、制御部21によって通知された2個のアドレス
の範囲に含まれる走行区間を走行区間毎実行回数記憶部
6の走行区間列記憶域60の中から選択し、該当する走
行区間の実行回数(走行区間毎実行回数列記憶域62)
の1だけ加算する。このとき、制御部21によって通知
された2個のアドレスの範囲に含まれる走行区間が1個
以上の場合もあるため、それぞれの走行区間に対し実行
回数を1だけ加算することになる。
Next, the operation of the method for measuring the number of program instruction executions of this embodiment configured as described above will be explained. First, a travel section setting instruction for the measurement target program 40 is input from the input device 1 . As a result of analyzing the input content, the input information analysis unit 20 interprets the input as an instruction to set a travel section for the measurement target program 40 and notifies the control unit 21 of the result. This notification enters the instruction word analysis section 22 through the control section 21. With this notification, the instruction word analysis unit 22
0 execution start address P0 and branch instruction positions B1 and B2
, B3, B4,... and branch destinations P1, P2, P3, P4,...
A running section P0 to B1, B1+1,
P1-1, P1~B2-1, P2~B2, B2+1~B
3, B3+1~P3-1, P3~B4, B4+1~P4
-1, . Further, the execution number string storage area 62 for each traveling section is initialized to zero. Next, assuming that the priority level of the measurement target program 40 is 1, priority level number 1 is input from the input device 1. The input information analysis section 20 notifies the control section 21 of the input priority level number 1. Upon receiving this notification, the control unit 21 activates the branch instruction interrupt mechanism 30 by setting the priority level number 1 to the branch instruction interrupt mode. At the same time, the control unit 21 also initializes the post-branch address 51 corresponding to priority level number 1 in the post-branch address storage unit 5 to zero. Thereafter, when the measurement target program 40 is started on the main storage device 4 and the branch instruction of the measurement target program 40 is executed, the branch instruction interrupt mechanism 30 of the central processing unit 3
A branch instruction interrupt is generated at the branch destination address specified by the branch instruction, and this branch instruction interrupt is reported to the control unit 21 of the program instruction execution count measuring device 2. Based on this report, the control unit 21 determines the priority level number 1, the pre-branch address which is the address of the branch instruction itself that caused the branch instruction interrupt in the measurement target program 40, and the post-branch address which is the branch destination due to this instruction. You can know. Based on this reported priority level number 1, the control unit 21:
The contents of the post-branch address 51 corresponding to priority level number 1 in the post-branch address storage unit 5 can be extracted, and the extracted address and the pre-branch address at this branch instruction interrupt are sent to the execution count adding unit 24. and instructs addition of the number of executions for each travel section. Further, the post-branch address at this time is stored in the post-branch address 51 until the next branch instruction interrupt. Thereafter, the execution number adding unit 24 selects the traveling section included in the range of the two addresses notified by the control section 21 from the traveling section string storage area 60 of the execution number per traveling section storage section 6, Number of executions of the corresponding travel section (execution number column storage area 62 for each travel section)
Add only 1. At this time, since there may be one or more traveling sections included in the range of the two addresses notified by the control unit 21, the number of executions is added by 1 to each traveling section.

【0010】なお、制御部21は、分岐後アドレス51
がゼロで初期化されている最初の分岐命令割込み時には
、分岐命令割込機構30から通知された分岐後アドレス
を分岐後アドレス51に記憶するだけで、実行回数加算
部24に対し加算指示をしない。以上の動作を行なった
後制御部21は、測定対象プログラム40での分岐後ア
ドレスからの実行再開を分岐命令割込機構30に指示し
、次の分岐命令割込み待ちとなる。
Note that the control unit 21 controls the post-branch address 51
At the time of the first branch instruction interrupt where is initialized to zero, the post-branch address notified from the branch instruction interrupt mechanism 30 is simply stored in the post-branch address 51, and no instruction to add is given to the execution count adding unit 24. . After performing the above operations, the control unit 21 instructs the branch instruction interrupt mechanism 30 to resume execution from the post-branch address in the measurement target program 40, and waits for the next branch instruction interrupt.

【0011】図2は、プログラム命令実行数測定装置2
が行なう走行区間毎実行回数の加算動作を、測定対象プ
ログラム40の実行開始アドレスP0からアドレスP4
までのルーチンを例にとって、具体的に説明するための
関連図である。ここで、測定対象プログラム40のアド
レスP0からアドレスP4までのルーチンは、走行区間
P0〜B1,B1+1〜P1−1,P1〜P2−1,P
2〜B2,B2+1〜B3,B3+1〜P3−1,P3
〜B4,B4+1〜P4−1とを含んでいる。
FIG. 2 shows an apparatus 2 for measuring the number of executed program instructions.
The addition operation of the number of executions for each running section is performed from the execution start address P0 of the measurement target program 40 to address P4.
FIG. 3 is a related diagram for specifically explaining the routines up to now as an example. Here, the routine from address P0 to address P4 of the measurement target program 40 is the running section P0 to B1, B1+1 to P1-1, P1 to P2-1,
2~B2, B2+1~B3, B3+1~P3-1, P3
~B4, B4+1~P4-1.

【0012】まず、測定対象プログラム40の実行開始
アドレスP0に動作のため制御が渡されると、分岐命令
割込機構30によって分岐命令割り込みが発生し、プロ
グラム命令実行数測定装置2(の制御部21)が分岐命
令割込みによって動作する。プログラム命令実行数測定
装置2(の制御部21)は、このとき分岐後アドレス5
1がゼロで初期化されているため、分岐命令割込機構3
0がら通知される分岐後アドレスP0を分岐後アドレス
51に記憶するだけで、分岐後アドレスP0からの実行
再開を分岐命令割込機構30に指示し、次の分岐命令割
込み待ちとなる。
First, when control is passed to the execution start address P0 of the program to be measured 40 for operation, a branch instruction interrupt is generated by the branch instruction interrupt mechanism 30, and the control unit 21 of the program instruction execution count measuring device 2 is generated. ) is activated by a branch instruction interrupt. At this time, the program instruction execution number measuring device 2 (control unit 21)
Since 1 is initialized with zero, branch instruction interrupt mechanism 3
By simply storing the post-branch address P0 notified from 0 in the post-branch address 51, it instructs the branch instruction interrupt mechanism 30 to resume execution from the post-branch address P0, and waits for the next branch instruction interrupt.

【0013】次にアドレスB1での最初の分岐命令が実
行され、分岐先であるアドレスP1で分岐命令割込みが
発生し、プログラム命令実行数測定装置2(の実行回数
加算部24)は分岐命令割込機構30から通知される分
岐前アドレスB1とこのとき分岐後アドレス51に記憶
しているアドレスP0との範囲(アドレスP0からアド
レスB1まで)に含まれる走行区間を走行区間毎実行回
数記憶部6(の走行区間列記憶域60)の中から選択し
、該当する走行区間P0〜B1の実行回数(走行区間毎
実行回数列記憶域61)を1だけ加算することになる。 分岐後アドレスP1は、次の分岐命令割込み時まで分岐
後アドレス51に記憶しておく。
Next, the first branch instruction at address B1 is executed, a branch instruction interrupt occurs at address P1, which is the branch destination, and the program instruction execution number measuring device 2 (execution number adding unit 24) calculates the branch instruction interrupt. The number of execution times storage unit 6 stores the running section for each running section, which is included in the range (from address P0 to address B1) between the pre-branch address B1 notified from the branching mechanism 30 and the address P0 stored in the post-branch address 51 at this time. (running section string storage area 60), and adding 1 to the number of executions of the corresponding driving section P0 to B1 (running section string storage area 61). The post-branch address P1 is stored in the post-branch address 51 until the next branch instruction interrupt.

【0014】次の分岐命令割込みは、アドレスB2での
分岐命令が実行され、分岐先であるアドレスP2で発生
する(なお、アドレスB2での分岐命令は、最初の実行
では分岐条件が満足されアドレスP2に分岐、2回目の
実行では分岐条件不一致でアドレスB2+1の命令を実
行するものとして説明する)。このときP1〜B2が範
囲となり、この範囲に含まれるのは走行区間P1〜P2
−1とP2〜B2の2個であり、それぞれの走行区間に
対し実行回数を1だけ加算することになる。以下、アド
レスB3,B4の分岐命令の実行によってそれぞれアド
レスP3,P4で分岐命令割込みが発生し、このときプ
ログラム命令実行数測定装置2(の実行回数加算部24
)によって走行区間P1〜B2,B2+1〜B3,P3
〜B4の実行回数が1だけ加算されることになる。
The next branch instruction interrupt occurs when the branch instruction at address B2 is executed and occurs at address P2, which is the branch destination. The following description assumes that the program branches to P2, and in the second execution, the instruction at address B2+1 is executed because the branch condition does not match). At this time, P1 to B2 becomes the range, and this range includes the traveling section P1 to P2.
-1 and P2 to B2, and 1 is added to the number of executions for each travel section. Hereinafter, branch instruction interrupts occur at addresses P3 and P4 due to the execution of the branch instructions at addresses B3 and B4, respectively, and at this time, the execution number addition unit 24 of the program instruction execution number measuring device 2
) depending on the traveling section P1-B2, B2+1-B3, P3
The number of executions of ~B4 is incremented by 1.

【0015】なお、分岐命令割込み時に分岐命令割込機
構30から通知されるのは、分岐命令自身のアドレスと
分岐命令の分岐先アドレスの他に、測定対象プログラム
40の優先レベル番号1(図示していない)もあり、こ
の優先レベル番号1によって分岐後アドレス51が選択
可能となる。
[0015] At the time of a branch instruction interrupt, the branch instruction interrupt mechanism 30 notifies the address of the branch instruction itself and the branch destination address of the branch instruction, as well as the priority level number 1 (not shown in the figure) of the program to be measured 40. This priority level number 1 allows the post-branch address 51 to be selected.

【0016】最初に測定が終了し、優先レベル番号1の
分岐命令割込みモード解除指令が入力装置1から入力さ
れる。入力情報解析部20は、この入力された優先レベ
ル番号1に対する分岐命令割込みモード解除指令を制御
部21に通知する。この通知を受けた制御部21は、優
先レベル番号1の分岐命令割込みモードを解除して、分
岐命令割込機構30を停止するとともに、優先レベル番
号1に対する測定結果を編集出力するように測定結果編
集出力部25に指示する。この指示を受けた測定結果編
集出力部25は、走行区間毎実行回数記憶部6をもとに
、測定結果リスト70を出力装置7に出力する。測定結
果リスト70は、走行区間毎実行回数記憶部6の走行区
間列記憶域60と走行区間内命令数記憶域61と走行区
間毎実行回数列記憶域62の内容に加え、これら情報を
もとに走行区間毎命令実行数とこの走行区間毎命令実行
数がプログラム全体に占める割合とが算出され編集出力
されたものである。
First, the measurement is completed, and a branch instruction interrupt mode release command with priority level number 1 is input from the input device 1. The input information analysis unit 20 notifies the control unit 21 of the branch instruction interrupt mode release command for the input priority level number 1. Upon receiving this notification, the control unit 21 cancels the branch instruction interrupt mode of priority level number 1, stops the branch instruction interrupt mechanism 30, and edits and outputs the measurement results for priority level number 1. The editing output unit 25 is instructed. Upon receiving this instruction, the measurement result editing/output section 25 outputs a measurement result list 70 to the output device 7 based on the number-of-executions storage section 6 for each travel section. The measurement result list 70 is based on the information in addition to the contents of the running section column storage area 60, the number of instructions within a running section storage area 61, and the execution number string storage area 62 for each running section of the execution number storage unit 6 for each running section. The number of commands executed per traveling section and the proportion of the number of commands executed per traveling section to the entire program are calculated and edited and output.

【0017】なお、分岐後アドレス記憶部5内の分岐後
アドレスは優先レベル番号1に対応させて(分岐後アド
レス51,52,…,5nと、優先レベル番号に対応)
記憶できるため、以上述べた優先レベル番号1で走行す
る測定対象プログラムだけでなく、優先レベル番号1以
外で走行する測定対象プログラムも測定することが可能
なことは明白である。さらに、ある優先レベル番号単独
の測定だけでなく、2個以上の優先レベル番号の測定対
象プログラムを同時に測定することも可能である。
Note that the post-branch address in the post-branch address storage unit 5 corresponds to the priority level number 1 (post-branch addresses 51, 52, . . . , 5n correspond to the priority level number).
Since it can be stored, it is clear that it is possible to measure not only the program to be measured running at priority level number 1 described above, but also the program to be measured running at a priority level other than number 1. Furthermore, it is possible not only to measure a certain priority level number alone, but also to simultaneously measure measurement target programs of two or more priority level numbers.

【0018】[0018]

【発明の効果】以上説明したように、本発明は、分岐命
令割込み手段と命令語解析手段とを利用することにより
、つぎのような効果を奏する。
As explained above, the present invention achieves the following effects by utilizing the branch instruction interrupt means and the instruction word analysis means.

【0019】*測定領域(走行区間)の設定が自動的に
行なわれるため、測定が簡単かつ早い。
*Since the measurement area (traveling section) is automatically set, measurement is simple and quick.

【0020】*プログラムの内容を全く知らなくとも測
定することができる。
*Measurement can be performed without knowing the contents of the program at all.

【0021】*測定のための時間は、机上計算の場合に
比較して大幅に減少する。
*The time required for measurement is significantly reduced compared to the case of theoretical calculations.

【0022】*編集出力される測定結果リストは、単に
実行される命令の合計数だけでなく、プログラム内の特
に知りたい領域(走行区間)の命令実行数とこの命令実
行数がプログラム全体に占める割合も出力される。プロ
グラムの性能向上を要求された場合、負荷の高い箇所に
ポイントをおいて改善する。したがって、本測定結果リ
ストは大変参考になる。
*The measurement result list that is edited and output shows not only the total number of executed instructions, but also the number of executed instructions in the area (running section) in the program that you are particularly interested in, and the number of executed instructions in the entire program. The percentage is also output. If you are asked to improve the performance of a program, focus on areas with high load and make improvements. Therefore, this list of measurement results is very helpful.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

【図2】図1中のプログラム命令実行数測定装置が行な
う走行区間毎実行回数の加算動作を説明するための関連
図である。
FIG. 2 is a related diagram for explaining an operation of adding the number of executions for each traveling section, which is performed by the program instruction execution number measuring device in FIG. 1;

【符号の説明】[Explanation of symbols]

1    入力装置 2    プログラム命令実行数測定装置3    中
央処理装置 4    主記憶装置 5    分岐後アドレス記憶部 6    走行区間毎実行回数記憶部 7    出力装置
1 Input device 2 Program instruction execution count measuring device 3 Central processing unit 4 Main storage device 5 Post-branch address storage unit 6 Execution count storage unit for each running section 7 Output device

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  分岐命令の実行により分岐後最初の命
令が実行される前に、当該分岐命令を含むプログラムの
走行の優先レベルと分岐命令自身のアドレスを示す分岐
前アドレスと分岐命令の分岐先アドレスを示す分岐後ア
ドレスとを保持して内部割込みを発生させかつ該内部割
込みが一個以上の前記優先レベルごとに発生できるよう
な分岐命令割込み手段と、該分岐命令割込み手段の起動
および停止を行なうための分岐命令割込みモード設定・
解除手段と、前記優先レベルに対応させて前記分岐後ア
ドレスを記憶する分岐後アドレス記臆手段と、プログラ
ム内を探索し分岐命令の位置と当該分岐命令の分岐先ア
ドレスに着目した走行区間を設定しつつ当該走行区間内
の命令の個数を解析する命令解析手段と、分岐命令割込
み毎に前記分岐命令割込み手段から通知される分岐前ア
ドレスと前記分岐後アドレス記臆手段により当該分岐命
令割込みの一度前の分岐命令割込み時に記憶されていて
当該分岐命令割込み時の優先レベルに対応の分岐後アド
レスとで示される範囲に含まれる前記走行区間に対し実
行回数を加算する走行区間実行回数加算手段と、前記命
令解析手段により設定された走行区間と当該走行区間内
の命令の個数に加え前記走行区間毎実行回数加算手段に
より加算される走行区間毎の実行回数とを記憶する走行
区間毎実行回数記憶手段と、前記走行区間毎実行回数記
憶手段により記憶された走行区間と走行区間毎命令数と
走行区間毎実行回数とを編集出力するとともに当該記憶
情報により走行区間毎命令実行数と当該走行区間毎命令
実行数が当該走行区間を含むプログラム全体に占める割
合とを算出しつつ編集出力する測定結果編集出力手段と
を具備することを特徴とするプログラム命令実行数測定
方式。
Claim 1: Before the first instruction after a branch is executed by executing a branch instruction, the execution priority level of the program including the branch instruction, the pre-branch address indicating the address of the branch instruction itself, and the branch destination of the branch instruction. A branch instruction interrupt means that holds a post-branch address indicating an address and generates an internal interrupt, and the internal interrupt can be generated for each of one or more of the priority levels, and starts and stops the branch instruction interrupt means. Branch instruction interrupt mode settings for
a release means, a post-branch address storage means for storing the post-branch address in correspondence with the priority level, and a running section that searches within the program and focuses on the position of the branch instruction and the branch destination address of the branch instruction. instruction analysis means for analyzing the number of instructions within the running section, and a pre-branch address notified from the branch instruction interrupt means for each branch instruction interrupt, and a post-branch address recording means to determine the number of instructions in the branch instruction interrupt. A running section execution number adding means for adding the number of execution times to the running section that is stored at the time of the previous branch instruction interrupt and is included in the range indicated by the post-branch address corresponding to the priority level at the time of the branch instruction interrupt; Execution count storage means for each running section stores the running section set by the command analysis means and the number of instructions in the running section, as well as the number of executions for each running section added by the running section adding number of executions for each running section. Then, the traveling section, the number of commands per traveling section, and the number of executions per traveling section stored by the storage means for the number of executions per traveling section are edited and outputted, and the number of commands executed per traveling section and the number of commands for each traveling section are output based on the stored information. A method for measuring the number of program command executions, characterized by comprising a measurement result editing and outputting means for editing and outputting a ratio of the number of executions to the entire program including the running section.
【請求項2】  前記走行区間毎実行回数記憶部が、プ
ログラムの実行開始アドレスと分岐命令の位置と分岐先
とによって区切られる走行区間列記憶域と、走行区間内
での命令数を記憶する走行区間内命令数記憶域と、走行
区間単位でみた実行回数が累積記憶さえる走行区間毎実
行回数列記憶域とで構成されることを特徴とする請求項
1記載のプログラム命令実行数測定方式。
2. The number-of-execution-per-traveling section storage unit includes a traveling section column storage area delimited by a program execution start address, a position of a branch instruction, and a branch destination, and a traveling section storing the number of instructions within a traveling section. 2. The method for measuring the number of executed program instructions according to claim 1, comprising a storage area for the number of instructions executed within a section, and a storage area for a number of executions per traveling section in which the number of executions per traveling section is cumulatively stored.
JP3002508A 1991-01-14 1991-01-14 System for measuring number of executed program instruction Pending JPH04241637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3002508A JPH04241637A (en) 1991-01-14 1991-01-14 System for measuring number of executed program instruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3002508A JPH04241637A (en) 1991-01-14 1991-01-14 System for measuring number of executed program instruction

Publications (1)

Publication Number Publication Date
JPH04241637A true JPH04241637A (en) 1992-08-28

Family

ID=11531312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3002508A Pending JPH04241637A (en) 1991-01-14 1991-01-14 System for measuring number of executed program instruction

Country Status (1)

Country Link
JP (1) JPH04241637A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010001766A1 (en) * 2008-07-02 2010-01-07 国立大学法人 東京工業大学 Execution time estimation method, execution time estimation program, and execution time estimation device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010001766A1 (en) * 2008-07-02 2010-01-07 国立大学法人 東京工業大学 Execution time estimation method, execution time estimation program, and execution time estimation device
US8448140B2 (en) 2008-07-02 2013-05-21 Tokyo Institute Of Technology Execution time estimation method and device
JP5403760B2 (en) * 2008-07-02 2014-01-29 国立大学法人東京工業大学 Execution time estimation method, execution time estimation program, and execution time estimation apparatus

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