JPS63300334A - Measurement system for number of times of instruction execution of program - Google Patents

Abstract

PURPOSE:To obtain reference for the performance improvement of a program (specially, a control program) by outputting not only the total number of instructions which are executed, but also the number of instructions which are executed by the kinds of the instructions and by priority levels to a list to be edited and outputted. CONSTITUTION:A measurement result editing and output part 23 outputs the measurement result list 71 which is so edited that the total of execute instructions and the numbers of times of execution by the kinds of the instructions are known according to the contents of an instruction execution frequency storage array 51 to an output device 7. Further, instruction execution frequency storage arrays for storing the numbers of times of execution by the instructions in an instruction execution storage part 5 are present by the priority levels and after-branch addresses can be stored in an after-branch address storage part 6 corresponding to the priority levels, so not only a program 41 to be measured which is run at a priority level 1, but also plural priority levels can be measured at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring the performance of a program in an information processing system, and particularly to a method for measuring the number of executed instructions of a program.

[Conventional technology]

Conventionally, in order to know the number of executed instructions of a program, which is a standard for program performance, calculations are performed on a desk while predicting the program execution process, or measurements are performed using a hardware monitor.

[Problem that the invention seeks to solve]

This requires a good understanding of the content of the program, and even for those in charge who have a good understanding of the content of the program, it requires a considerable amount of time. Furthermore, the method of measuring the number of instruction executions using a hardware monitor is generally not used by software engineers because preparation for measurement is troublesome.

An object of the present invention is to provide a method for measuring the number of instruction executions that can easily measure the number of instruction executions without knowing the contents of the program.

[Means for solving problems]

The method for measuring the number of instructions executed in a program according to the present invention is to generate an internal interrupt by holding the priority level, pre-branch address, and post-branch address before the first instruction after the branch is executed by executing a single branch instruction. A branch instruction interrupt means that can generate an internal interrupt for each priority level of one or more, a branch instruction interrupt mode setting canceling means for starting and stopping this branch instruction interrupt means, and a branch instruction interrupt mode setting canceling means for starting and stopping this branch instruction interrupt means, The post-branch address storage means stores the address, and the pre-branch address and post-branch address that are notified from the branch instruction interrupt means at the time of one branch instruction interrupt are stored at the time of the branch instruction interrupt just before this branch instruction interrupt. An instruction analysis means that searches for instructions existing in the range indicated by the post-branch address corresponding to the priority level at the time of a branch instruction interrupt and analyzes the number of each type of instructions; Instruction number storage means for accumulating and storing the number of each type in correspondence with each type of instruction and each priority level.

The present invention is characterized by comprising editing and outputting means for editing and outputting the number of each type of instructions cumulatively stored by the instruction number storage means for each priority level.

〔Example〕

Next, one aspect of the present invention will be explained with reference to examples.

FIG. 1 is a block diagram showing the structure of an embodiment of a method for measuring the number of executed instructions of a program according to the present invention. Referring to FIG. 1, the method for measuring the number of executed instructions in a 7° program consists of an input device l on which an input operation is performed, an input information analysis section 20, a control section 21, a command word analysis section 22, and a measurement result editing/output section. 2
3 and a program instruction execution count measuring device 2 including 1 and 1. A branch that holds a priority level, a pre-branch address, and a post-branch address and generates an internal interrupt before the first instruction after the branch is executed by executing the branch instruction. The central processing unit 3 including the instruction interrupt mechanism No. 30, and the measurement target programs 41, 42 .・・・
. , 4n.

An instruction execution number storage section 5 that stores the number of executions of each instruction corresponding to each priority level, and post-branch addresses 61, 62 . . . corresponding to each priority level. ..., 5n until the next branch instruction interrupt, and the measurement result list) 71.72. ....

7n is provided.

The instruction execution number storage unit 5 includes an instruction string 50 that indicates the distinction of instructions, and an instruction execution number storage column that corresponds to each priority level and corresponds to each instruction in the instruction string 50 and stores the number of executions of the instruction. 51, 52. ....

5n (corresponding to priority levels 1, 2, . . . n, respectively).

Note that at priority level 1, the measurement target program 41, instruction execution number storage column 51, post-branch address 61, and measurement result restore 1 are related, and at priority level 2, the measurement target program 42, instruction execution number storage column 52, and branching are related. The rear address 62 and the measurement result restore 2 are related. Therefore, at priority level n, the measurement target program 4n, the instruction execution count storage column 5n, the post-branch address 6n, and the measurement result restore n
will be related.

Next, the operation of the method for measuring the number of program instruction executions described above will be explained. Here, assuming that the program for measuring the number of executed instructions is the measurement target program 41, the priority level number 1 of the measurement target program 41 is input from the input device 1.

The input information analysis unit 20 notifies the input priority level number 1t to the control unit 21. Upon receiving this notification, the control unit 21 sets the priority level number 1 to the branch instruction interrupt mode, activates the 1 branch instruction interrupt mechanism 30, and executes the instruction in the instruction execution number storage unit 5 corresponding to the priority level number 1. The number storage column 51 and the post-branch address 61 in the post-branch address storage section 6 are initialized to zero. After that, the main memory 4
When the measurement target program 41 is started and a branch instruction is executed, the branch instruction interrupt mechanism 30 of the central processing unit 3
generates a branch instruction interrupt at the branch destination address to operate the control unit 21 of the program instruction execution count measuring device 2. The control unit 21 is notified by the 1-branch instruction interrupt mechanism 30 of the priority level number 1, the pre-branch address which is the address of the branch instruction itself in the measurement target telogram 41, and the post-branch address which is the branch destination of this branch instruction. Within the range from the address indicated by the content of the post-branch address 61 corresponding to the priority level number IK in the branch destination address memory 6 (address in the measurement target program 41) to the pre-branch address notified at the time of a branch instruction interrupt. Instructs the instruction word analysis unit 22 to analyze a certain instruction, and also stores the post-branch address notified at the interrupt of this branch instruction in the post-branch address 61 until the interrupt of the next branch instruction for priority level number 1. . Next, the instruction word analysis unit 22 analyzes the instructions within the range instructed by the control unit 21, and stores the analysis result (number of each type of instruction) in the instruction execution number storage column 51 corresponding to priority level number 1. Addition is made according to the type of instruction within. Note that the control unit 21 selects address 6 after 9 branches.
On the first branch instruction interrupt, 1 is initialized with zero.

By simply storing the post-branch address notified from the branch instruction interrupt mechanism 30 in the post-branch address 61, the instruction word analysis unit 2
Do not instruct 2 to analyze the command.

After performing the above operations, the control unit 21 instructs the branch instruction interrupt mechanism 30 to resume execution from the post-branch address in the measurement target program 41, and waits for the ninth branch instruction interrupt.

Here, referring also to FIG. 2, the range to be analyzed by the instruction word analysis unit 22 of the program instruction execution count measuring device 2 is from address PO to address P4 of the measurement target program 41.
The routine up to this point will be explained as an example.

In the measurement target program 41, addresses PO, PI
, P2. P3. P4 is the branch destination address of the branch instruction, and is the shore address Bl, B2 . B3. B4 is the address of the branch instruction itself. First, when a branch instruction (not shown) that branches to the address POK of the measurement target program 41 is executed, a branch instruction interrupt is generated by the 9 branch instruction interrupt mechanism 30, and the control unit 21 of the program instruction execution number measuring device 2 )
works.

The program instruction execution count measuring device 2 (control unit 21 thereof) stores the address PO notified from the branch instruction interrupt mechanism 30 in the post-branch address 61 (here, the operation procedure for the range before branching to the address PO will be explained). ).

Next, the branch instruction at address Bl of the measurement target program 41 is executed and a branch instruction interrupt occurs at address Pi, which is the 9th branch destination, and the program instruction execution number measuring device 2 (instruction word analysis unit 22) detects the branch instruction interrupt. The range (from address PO to address Bl) between the address B1 notified from the loading mechanism 3o and the address PO stored in the post-branch address 61 at this time (from address PO to address Bl) is analyzed, and the analysis results (for each type of instruction) are analyzed. ) is added in correspondence with the type of instruction in the instruction execution count storage column 51.

After that, the control unit 2 of the program instruction execution count measuring device 2
1) stores the address P1 notified together with the address B1 in the post-branch address 61.

Similarly, address B2. B3. By executing the branch instruction of B4, addresses P2. P3. A branch instruction interrupt occurs at P4, and at this time, the program instruction execution count measurement device 2 (instruction word analysis unit 22) analyzes the range from address Pi to address B2, and
These are the range from address P2 to address B3, and the range from address P3 to address B4. Note that when an 8-branch instruction interrupt occurs, the address of the 1-branch instruction itself (Bl, B2.B3.B4) is notified from the branch instruction interrupt mechanism 30.
and the branch destination address 2 of the branch instruction (PO, Pl, P2.P3
．． In addition to P4), there is also a priority level number (not shown) of the program to be measured 41, and this priority level number makes it possible to select the instruction execution number storage column 51 and the post-branch address 61.

Measurement for 4 programs to be measured has been completed.

A branch instruction interrupt mode release command with priority level number 1 is input from the input device 1 . The input information analysis unit 20 notifies the control unit 21 of the branch instruction interrupt mode release command for the input priority level number 1. Upon receiving this notification, the control unit 21 cancels the branch instruction interrupt mode of priority level number 1.

The branch instruction interrupt mechanism 30 is stopped (it will not be stopped if there is another priority level in the branch instruction interrupt mode), and the measurement result editing/output unit 23 is instructed to edit and output the measurement results for priority level number 1. . Upon receiving this instruction, the measurement result editing output unit 23 edits the measurement result restore 1 based on the instruction execution number storage column 51 so that the total number of executed instructions and the number of executions for each type of instruction can be determined. is output to the output device 7.

Further, an instruction execution number storage column for storing the number of executions for each instruction in the instruction execution number storage unit 5 exists for each priority level, and the post-branch address is also stored in the post-branch address storage unit 6 in correspondence with the priority level. Because I can.

It is possible not only to measure only the program to be measured 41 running at priority level 1 described above, but also to simultaneously measure multiple priority levels.

〔Effect of the invention〕

As explained above, since the present invention measures the number of executed instructions of a program using a single branch instruction interrupt, it can be measured without knowing the contents of the program at all, and the measurement procedure is simple and straightforward. .

Furthermore, the time required for measurement is significantly reduced compared to when calculating on a desk. Also, the list that is edited and output includes not only the total number of executed instructions.

Since the number of executed instructions is output for each type of instruction and each priority level, it is very useful when improving the performance of a program (especially a control program).

Remaining days below

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a related diagram for specifically explaining the range analyzed by the instruction word analysis section of the program instruction execution count measuring device. In fig. DESCRIPTION OF SYMBOLS 1... Input device, 2... Program instruction execution number measuring device, 3... Central processing unit, 4... Main storage device, 5
. . . Instruction execution number storage unit, 6 . . . Post-branch address storage unit. 7... Output device, 20... Input information analysis section, 21.
...Control unit, 22...Instruction word analysis unit, 23...Measurement result editing output unit, 30...Branch instruction interrupt mechanism, 41,
42, 4n...Program to be measured, 50...Instruction string, 51,52゜5n...Function instruction execution number memory string t6
1+62+6n...address after branch, 71j72,7
n: Measurement result list. Figure 1

Claims (1)

[Claims] 1. Before the first instruction after a branch is executed by executing a branch instruction, the priority level of the program including the branch instruction, the pre-branch address which is the address of the branch instruction itself, and the branch address which is the branch destination address of the branch instruction. a branch instruction interrupt means for generating an internal interrupt while holding a subsequent address and generating the internal interrupt for each of the one or more priority levels; and a branch instruction interrupt for starting and stopping the branch instruction interrupt means. mode setting canceling means; post-branch address storage means for storing the post-branch address in correspondence with the priority level; and storage of the pre-branch address and the post-branch address notified from the branch instruction interrupt means at the time of a branch instruction interrupt. The means searches for an instruction existing in the range indicated by the post-branch address that is stored at the time of a branch instruction interrupt just before the branch instruction interrupt and corresponds to the priority level at the time of the branch instruction interrupt, and determines the type of the instruction. an instruction analysis means for analyzing the number of each type of instruction, and an instruction number storage means for accumulating and storing the number of each type of instruction, which is the analysis result of the instruction analysis means, in correspondence with each type of instruction and each priority level; A method for measuring the number of executed instructions of a program, comprising: editing and outputting means for editing and outputting the number of each type of instructions cumulatively stored by the instruction number storage means for each priority level.