JPS59146342A - Loop control system - Google Patents

Abstract

PURPOSE:To improve the operation speed, by executing the operation control and the loop control independently of each other. CONSTITUTION:By the execution of a loop set instruction, the first operand is stored in a loop final address storage register 5. The second operand is stored in a loop counter 3, and the third operand is stored in a branch destination address storage register 2. Then, an address coincidence detector 4 becomes operation state. The detector 4 checks always the coincidence between contents of a counter 1 and the register 5 and counts down the value of the loop counter 3 by one if they coincide with each other. When the result is not zero, the output of the branch destination address register 2 is set to the counter 1 to execute the loop. Since the instruction in the loop final address can be executed in an operation processing part 6 during this operation, the loop control and the operation processing are executed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION (Prior Art) With the advancement of digital computers, computers have come to be used in the fields of signal processing and true image processing. Applications in such fields generally involve performing simple repetitive operations on large amounts of data. Therefore,
The processing time for such processing is expressed as in the following equation.

Processing time = calculation time for 1 data × amount of data In applications where the amount of data is often determined in advance, in order to reduce the processing time for such applications, it is necessary to increase the calculation speed for 1 data. It becomes necessary to speed up.

FIG. 1 shows an example of a program for repeat operation 9 in such an application using a conventional divider. In (2), the number of loops is set to 10 in the C register. (k゛) is an arithmetic unit that handles processing for one data. (2) subtracts 1 from the value of the C register.

(2) indicates that if the result of the 1jt calculation in (2) is not O, the process branches to LOOP. In this kind of programming power, there is not only ■ but also ■ in the processing of one data.

■It also includes a trench.

In other words, in one data processing, not only the true calculation time but also the time for loop control is necessary, and especially when the processing part is simple, the proportion of wasted time for loop control is large. It has the disadvantage of being

(Object of the Invention) An object of the present invention is to provide a loop control method that improves calculation speed by eliminating the drawbacks of the prior art.

The method of the present invention is a digital meter that controls the program by a program counter, with a loop count of 2.
Loop count storage means 2 for storing the contents of a loop set instruction specifying a public address and a loop final address, respectively; 2 public address storage means and a loop final address storage means; and the contents of the program counter match the loop final address. and loop end detection means for detecting that the contents of the program counter match the number of loops. and after specifying the final address of the loop to each storage means, the loop end detection means is actuated by a match signal from the address match detection means, and the branch destination address is set in the program counter according to the detection content of the loop end detection means. It consists of performing sirug control by determining whether or not to do so.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is an example of a program for repeated calculations according to an embodiment of the present invention, and FIG. 3 is a block diagram showing a configuration according to an embodiment of the present invention. In Figure 2, ■ indicates a loop set instruction, where the first operand is the loop final address and the second operand is the loop set instruction.
The operand indicates the number of loops, and the third operand indicates the branch destination address. ■ indicates a calculation section. In FIG. 3, 1 is a program counter, 2 is a branch destination address storage register, 3 is a loop counter, D is an address-paper detector, 5 is a loop final address storage register, and 6 is an arithmetic processing section.

Next, the operation of this embodiment will be explained. By executing the instruction shown in Figure 2, the value of the first operand is stored in the loop final address storage register S, the content of the second operand is stored in the loop counter 3, and the content of the third operand is the branch destination address. Stored in storage register 2 and at address -
The paper detector 4 becomes operational. It is constantly checked whether the contents of the address/paper detector 4, program counter] and the loop final address storage register 5 match, and if they match, the value of the loop counter 3 is decremented by one. If the result of the operation is not 0, the output of the branch destination address storage register 2 is set in the program counter 1, thereby performing a loop. In this embodiment, the loop counter 3 functions as loop count storage means and loop end detection means.

During this operation, the arithmetic processing section 6 can execute the instruction at the final address of the loop, so that the loop control and the simulation processing are executed in parallel. When the value of the loop counter 3 is decremented and becomes 0, the program exits from the loop according to the normal program counter operation. At this time, the address match detector 4 stops.

(Effects of the Invention) As described in detail above, according to the present invention, since calculation control and loop control can be executed independently, one data processing time becomes purely calculation time, and when calculation is relatively simple, The effect of significantly improving processing speed can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a program for a conventional iterative operation p.
FIG. 2 is a diagram showing an example of a program for repeated calculations according to an embodiment of the present invention, and FIG. 3 is a block diagram showing a configuration according to an embodiment of the present invention. In the figure, ■... Roof count setting command, ■
...Arithmetic unit, ■...Register decrement instruction, ■...Conditional branch instruction, ■...
... Loose set instruction, ■ ... Arithmetic section, 1.
...Program counter, 2...Branch destination address storage register, 3...Loop...
Counter, 4...Address detector, 5...
...Loop final address storage register, 6...
- Arithmetic processing unit. //' Even more. Agent Patent Attorney Susumu Uchihara 2- ・;
C------------1■ JNZ LOOp -1------1-■Fall/Closed LODPSET LODP END/C,L
OOP -1-■Second flash

Claims (1)

[Claims] In a digital calculator that controls a program using program color/reference, the loop count 1 branch address and loop final address are specified among the instructions.
4'c Loop count storage means for storing 2 common address storage means and loop final address storage means, address coincidence detection means for detecting that the contents of the program counter match the loop final address, and the program counter loop end detection means → for detecting that the contents of the loop match the number of loops; and then actuating the loop end detecting means in response to a match signal from the address match detecting means, and determining whether or not to set the branch destination AT and RES in the program counter based on the detection contents of the loop end detecting means. A loop control method characterized by performing loop control.