JPH0679271B2 - Loop control circuit - Google Patents

Description

The present invention relates to a microprocessor having a loop function, and more particularly to a loop control circuit suitable for multiple loop control.

[Prior Art] As shown in FIG. 2, a conventional loop control circuit includes a register 1 for storing the start address of a loop and a loop counter 2 for counting and storing the number of loops and determining a loop end condition.
And a stack area 4 for saving and storing the contents of both the register 1 and the counter 2. At the time of multiple loop control, the head address in the register 1 and the number of loops in the counter 2, that is, two loop control data are sequentially saved in series in the stack area 4.

[Problems to be Solved by the Invention] As described above, in the conventional loop control circuit, both loop control data of the loop start address and the loop count are separately saved / restored during the multiple loop control. The microinstruction indicating the head (hereinafter referred to as a loop top instruction) and the instruction for determining the end of the loop (hereinafter referred to as a loop end instruction) are each configured by two instructions, or one instruction performs data transfer twice. It is necessary to add a circuit for this, and the program description becomes complicated as the number of stages of the multiple loop increases, and there are problems that the data transfer cycle increases and the execution speed decreases.

An object of the present invention is to enable transfer of both loop control data in one loop transfer cycle so that one loop control instruction can be executed.

[Means for Solving the Problems] In order to achieve the above object, the present invention, as shown in FIG. 1, sets a loop start address in a control circuit of a micro control processor for controlling operation by a micro instruction. Holding means 1 for storing, counting means 2 for counting / storing the number of loops and detecting end of loop, save storage means 4 for storing both loop control data of the start address and the number of loops at the time of save, the save At times, the two data are connected in parallel and stored in the storage means, and at the time of restoration, the both data are read in parallel from the storage means and are divided and returned to the holding means and the counting means. Is provided, and both of the above-mentioned data are transferred at the same time.

A register can be used for the holding means 1, a counter can be used for the counting means 2, and a data selector can be used for the data connecting / dividing means 3.

More specifically, the loop control circuit according to the present invention stores a loop start address register for storing a start address of a loop and a loop count in a loop control operation of a micro control processor for controlling operation by a micro instruction of a micro program. Loop count register, a stack memory for storing both loop control data of the loop start address and loop count in parallel at the time of saving, and the loop count set in the loop count register is decremented by 1 for each loop passage A decrementer for updating the value of the number of times register, and a loop end determination means for determining the end of the loop by determining whether the value of the loop number register has reached a predetermined value as a result of the subtraction by the decrementer, A program counter that specifies the address of the micro instruction, and the program An incrementer that sequentially updates the value of the counter and a sequencer control unit that controls the operation of the loop control circuit are provided, and the sequencer control unit, when a loop top instruction indicating the start of the loop appears during program processing, Both loop control data in the loop head address register and the loop count register at that time are stored in parallel in the stack memory, and the loop head address and the loop count related to the loop top instruction are respectively stored in the loop head address register and When the loop end instruction indicating the end of the loop is stored in the loop count register, the loop end determining means makes a determination, and when the loop processing is continued, the value of the loop start address register is written in the program counter and the loop is executed. Continue processing and end loop processing Sometimes it is the retracted immediately before the two-loop control data that so as to shift to execution of subsequent microinstruction is read out to the loop start address register and the loop count register in parallel from the stack memory.

[Operation] In the loop control circuit of the present invention, the loop start address data of the holding means and the loop count data of the counting means are
By passing through the data connecting / dividing means, it is saved as one data in the saving storage means at once, and at the time of restoration, both data are read out from the saving storage means at once and separated, and returned to the original holding means and counting means. I did it.

That is, in FIG. 1, in the case of multiple loop control,
Two loop control data (start address and loop count) of the outer loop for each loop top instruction of the inner loop are saved in parallel in the save storage means 4 via the data linking / dividing means 3 and returned to the outer loop. Sometimes data concatenation
Both loop control data are restored at once through the dividing means. The save storage unit 4 can handle the loop control data like other register save data.

Embodiments Embodiments of the present invention will be described below with reference to FIGS. 3, 4, and 5.

FIG. 3 shows an embodiment of the present invention, in which a loop head address register (holding means) 1 and a loop counter (counting means) are provided.
2, a main stack (save storage means) 4, and a selector (data connecting / dividing means) 5 for switching between loop control data and data 6 such as save data of general-purpose registers.

An example of the operation of the apparatus shown in FIG. 3 will be described with reference to FIG.

When a loop top instruction appears during program processing, the current loop control data is saved and new loop control data is stored in the head address register 1 and the loop counter 2. For example, at address a, the current loop control data is saved in the stack 4 to save it. Therefore, the selector 5 is switched from the data 6 side to the loop control data side, and the upper address register 1,
The data of the loop counter 2 is selected on the lower side. Thus, the linked data is stored in the stack 4. After that, the head address data (a + 1) is stored in the register 1 and the loop count data (32) is stored in the counter 2.

The loop top instruction is similarly processed at the address b while the processing from the address a + 1 is being executed. The loop control data stored in the register 1 and the counter 2 by the loop top instruction at the address a is saved in the stack 4, and the head address data (b + 1) is newly stored in the register 1 and the loop count data (2) is stored in the counter 2. Is stored.

With the loop end instruction at address c, the end determination is made based on the data in the loop counter 2. When it is determined that the loop has ended, the loop control data currently stored becomes unnecessary, and the data stored at the address a, that is,
The data saved at the address b is restored from the stack 4, and then the instruction address to be executed next is the address next to the loop end instruction, that is, the address c + 1.

When it is determined that the loop is continued in the above-described end determination, the loop counter 2 counts the loop, and the instruction address to be executed next is set as the loop start address (b + 1).
In this way, a loop is formed by repeatedly executing the instruction sandwiched between the loop top and loop end instructions a set number of times.

Similarly, the loop end instruction at the address d is also used to determine the end, and at the end of the loop, the loop control data stored before the address a is returned from the stack.

By performing the loop control as described above, it is possible to save and restore the loop control data at the start and end of the loop by one data transfer, respectively, which has the effect of improving the speed of the loop control.

FIG. 5 shows another embodiment of the present invention. When RAM is used for the data stack 4, the access time becomes slower than that of the register. Therefore, in this embodiment, a TOS (Top of Stack) register 13 is provided at the top of the stack to shorten the stack access time. Thus slow RAM
Speeding up by combining a register with a buffer and buffering data is generally known.

In this circuit, the TOS register 13 can be used as the loop head address register 1 and the loop count register 2a to facilitate the connection of both loop control data. Loop count register 2a, decrementer 2b, and comparator 2c
And constitute the counting means 2 of the present invention. Further, the program counter (PC) 9, the incrementer 8, and the selector 10 constitute a next address control circuit. The selector 5 constitutes the data connecting / dividing means 3 of the present invention similarly to the one shown in FIG. The selectors 5 and 10 are controlled by the sequencer control circuit 11. In addition, FIG. 5 shows an arithmetic logic unit (ALU) 12 and a general-purpose register 7.

Next, the operation of the circuit shown in FIG. 5 will be described. First, when the loop top instruction is given, the sequencer control circuit 11
The TOS register input selector 5 is switched and the value obtained by adding 1 to the contents of the program counter 9 by the incrementer 8 is TOS.
The data of the number of loops preset in the general-purpose register 7 is input to the lower side of the TOS register 13 in the upper side of the register 13. The contents of the TOS register 13 are saved in the stack 4 before the contents of the TOS register 13 are updated with this new data. In this way, the loop top instruction causes the start address of the loop and the loop count data to be stored in parallel in the TOS register 13.

Next, after execution of the instruction in the loop, when the loop end instruction is given, the comparator 2c judges the number of loops and gives the result to the sequencer control circuit 11. When it is determined that the loop has ended, the selector 5 selects the output of the incrementer 8,
Exit the loop and execute the next instruction. At this time, TO
The data previously saved from the stack 4 is recalled to the S register 13. Further, when the sequencer control circuit 11 determines that the loop continues, the selector 10 selects the address part of the TOS register 13, so that the head address of the loop can be input to the PC 9 and the loop can be returned to the head. At this time, TO
By switching the lower side of the S register input selector 5 to the output side of the decrementer 2b, the content of the loop counter 2 is decreased by 1.

As described above, according to the present embodiment, the number of registers can be reduced, and the data of the loop start address and the number of loops in the multiple loop can be saved in the stack 4 at once to improve the speed.

[Effects of the Invention] As described above, according to the present invention, the loop control data is transferred in parallel at the time of stack saving and restoration of the loop control data at the start and end of the loop.
It is now possible to transfer the start address and the loop count data divided into two times by one loop transfer, and there is an effect of improving the loop control speed especially in a multiple loop.

Further, since the conventional data transfer is performed twice, it is possible to perform one instruction in the present invention, which was conventionally two instructions for the loop top and loop end instructions at the start and end of the loop, and the program description is easy. There is also the effect of becoming.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a block diagram of a conventional loop control circuit, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is for explaining its operation. And FIG. 5 shows another embodiment of the present invention. 1 ... Loop start address register (holding means), 2 ... Loop counter (counting means), 3 ... Selector (data linking / dividing means), 4 ... Data stack (saving storage means).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazumi Kubota, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Microelectronics Equipment Development Laboratory (56) Reference JP 60-20242 ( JP, A)

Claims (3)

[Claims] 1. A loop control circuit of a microprocessor for controlling an operation by a micro instruction of a micro program, a loop start address register for storing a loop start address, a loop count register for storing a loop count, and the loop top. A stack memory that stores both the loop control data of the address and the loop count in parallel at the time of saving, and a decrementer that updates the value of the loop count register by subtracting 1 from the loop count set in the loop count register each time the loop passes. And a loop end judging means for judging the loop end by judging whether or not the value of the loop number register reaches a predetermined value as a result of the subtraction by the decrementer, and a program for designating the address of the micro instruction. The counter and the program that sequentially updates the value of the program counter. And a sequencer control means for controlling the operation of the loop control circuit. The sequencer control means, when a loop top instruction indicating the start of a loop appears during program processing, the loop top address register at that time. And storing both loop control data in the loop count register in parallel in the stack memory,
When the loop start address and the loop count related to the loop top instruction are stored in the loop start address register and the loop count register, respectively, and when a loop end instruction indicating the end of the loop appears,
The loop end judging means makes a judgment, and when the loop processing is continued, the value of the loop start address register is written in the program counter to continue the loop processing, and when the loop processing is completed, the both loop control data saved immediately before is stored in the loop control data. A loop control circuit, wherein the loop head address register and the loop count register are read in parallel from a stack memory and the subsequent micro instruction is executed. 2. A TOS register that holds the uppermost data of the stack memory is provided in the preceding stage of the stack memory, and one of the upper side and the lower side of the TOS register is the loop start address register and the other is the loop. The loop control circuit according to claim 1, wherein the loop control circuit is used as a frequency register. 3. The loop control circuit according to claim 1 or 2, wherein the stack memory is used as a save area for data other than the both loop control data.