JP2659603B2 - Arithmetic processing method and arithmetic processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to an arithmetic processing unit having a hardware swap function capable of executing a plurality of tasks in a time-division manner and performing a plurality of tasks in parallel. The present invention relates to an arithmetic processing method using.

[Conventional technology]

An arithmetic processing unit represented by a microcomputer.
As one of the methods of performing the parallel processing, there is a method of saving the contents of a register and a flag and switching tasks by software, which is realized by interrupt processing.
However, due to the overhead of interrupt processing,
Fast task switching is difficult. For this reason, a method has been conceived in which the number of tasks for which registers, flags, and the like are to be processed in parallel is prepared on hardware, and a plurality of tasks are executed by switching these.

FIG. 7 is a block diagram of a swap function part in a conventional processor of this type. In FIG. 7, an arithmetic processing unit capable of executing four tasks in parallel is assumed as an example.

In FIG. 7, a wait flag circuit 1 sets a flag indicating a task not to be operated. When the wait flag is set for a task, the process proceeds to the next task without performing the processing of the task.

The swap control circuit 2 is a logic circuit that determines the next task to be executed based on the currently executed task and the information of the wait flag in the wait flag circuit 1. The swap control circuit 2 outputs signals CPUS0 and CPUS1 indicating the state of the task.

FIG. 8 is a timing chart showing the timing of swap in a conventional arithmetic processing unit. In this figure, as an example, in an arithmetic processing unit that can execute four tasks A, B, C, and D in parallel, the timing when the wait flag is not set is shown, and the four tasks A, B, C, and D are shown. Are sequentially executed one by one in a time-division manner.

Thus, when swapping n tasks under hardware control, all tasks can be executed equally.

When the n tasks are swapped by hardware control as described above, there is an advantage that each task can be executed at the same rate. In addition, the swap for each instruction can execute each task equally, and macroscopically, the tasks appear to be executed in parallel, and the real-time property can be maintained.

However, considering an arithmetic processing unit that can execute the four tasks A, B, C, and D in parallel at the same rate, when the number of instructions constituting each of the four tasks A, B, C, and D is not the same,
For example, in the case where the number of instructions configuring tasks A and C is twice the number of instructions configuring tasks B and D, and tasks A and C must perform twice as many tasks as tasks B and D At the same execution ratio, tasks A, B, C and D are apparently processed in parallel in the first half as shown in FIG. For tasks B and D, 100% of the processing is completed at this stage, while for tasks A and C, only 50% of the processing is completed at this stage. In the latter half, the processing of tasks B and D has been completed, so that tasks B and D are set to wait by setting a wait flag, and the remaining 50% of tasks A and C are processed.

Thus, in the conventional arithmetic processing unit, tasks A, B, C,
Of D, only a certain task, for example, if you want to give priority to the processing of tasks A and C, and after the other tasks B and D finish processing and stop, the remaining processing of tasks A and C you want to give priority to It must be performed, during which time the next task following tasks B and D cannot be executed, and the real-time nature of parallel processing is lost. In other words, if the swap rate is fixed at the same rate, the next task cannot be executed immediately after one task is completed because of the priority of processing, and the processing efficiency is deteriorated due to waiting.

Therefore, for the purpose of solving the above problems, the following arithmetic processing methods have been proposed.

FIG. 1 is a block diagram of a swap function part of an arithmetic processing unit that executes the arithmetic processing method of the proposed example. First
In the figure, an arithmetic processing unit capable of executing four tasks in parallel is assumed as an example.

In FIG. 1, a wait flag circuit 1 is a circuit for setting a flag indicating a task not to be operated. When the wait flag is set for a task, the process proceeds to the next task without performing the processing of the task.

Each of the counters 3, 4, 5, and 6 corresponds to a register. Each of the counters 3, 4, 5, and 6 has a down counter configuration that counts the number of instruction executions of tasks A, B, C, and D by a signal LAST generated when one instruction is executed. Yes, the number of instruction executions is preset according to the ratio of the number of instruction executions for each task A, B, C, D. When it becomes 0, an overflow signal is output.

The swap control circuit 2 calculates the current execution timing, the information of the wait flag in the wait flag circuit 1 and the overflow signals of the counters 3, 4, 5, and 6,
This is a logic circuit that determines the task to be executed next. The swap control circuit 2 outputs signals CPUS0 and CPUS1 indicating the state of the task.

2 and 3 are timing charts corresponding to FIGS. 8 and 9 of the conventional example, respectively. In these figures,
FIG. 2 is a timing chart of swapping when the execution ratio of tasks A and C is set to twice that of tasks B and D when swapping tasks A, B, C, and D with the same processing amount as the conventional example. FIG. 3 shows an overall timing chart.

FIG. 2 shows a state in which a cycle in which task A executes two instructions, task B executes one instruction, task C executes two instructions, and task D executes one instruction.
As shown in FIG. 2, when the processes of the tasks A, B, C, and D are performed in a time-division manner, the execution of the tasks A, B, C, and D ends at substantially the same time as shown in FIG. become. In FIG. 3, the processing execution density is made to correspond to the shaded area density.

With this setting, when tasks B and D end, processing of tasks A and C ends, so that processing of all tasks is performed uniformly and real-time processing of parallel processing is maintained. can do.

As described above, by providing a counter for each of the n tasks, if the execution ratio of the tasks can be changed arbitrarily, the execution end of each task processed in parallel regardless of the processing amount of each task is completed. The timings of the time points can be aligned, and even when it is desired to execute a specific task with priority, macroscopically, each task can be uniformly processed in parallel while maintaining real-time properties.

[Problems to be solved by the invention]

In the above proposed example, by changing the execution ratio of tasks, when only a specific task is to be executed preferentially, by setting the execution ratio to the counter of each task, it is possible to execute uniformly and macroscopically Can be.

FIG. 5 shows an arithmetic processing unit that can execute four tasks A, B, C, and D at the same time.
It shows the timing of one cycle of swapping when the execution ratio is set such as four instructions for tasks B and C and two instructions for task D. In the configuration of the proposed example, the swap executes task A by 8 instructions, executes task B by 4 instructions, executes task C by 4 instructions, and executes task D by 2 instructions.
The execution of an instruction is one cycle, and the processing of each of the tasks A, B, C, and D is executed by repetition of this cycle, and real-time performance is maintained.

However, from a microscopic perspective of one cycle,
The processing of each task A, B, C, D is performed as described above.
C and D are hardened and executed, which is not preferable from the viewpoint of processing uniformity.

For example, consider the reaction speed of an interrupt. For example, if the interrupt request of the task D occurs while the task A of the time 1 on the vertical axis is being executed, the interrupt is not accepted until the next time when the task D is executed is not waited for 16 instructions. However, there was a problem that the response speed to the interrupt was slow.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an arithmetic processing method capable of uniformly performing processing of each task, maintaining real-time properties of parallel processing, and increasing a response speed to an interrupt.

[Means for solving the problem]

An arithmetic processing method according to the present invention is an arithmetic processing method for executing n tasks in parallel by switching and executing the n tasks in a time-sharing manner by a hardware controlled swap function. The ratio of the number of instruction executions is arbitrarily programmable by a register, and the task is switched in units of one instruction according to the ratio of the number of instruction executions for each task. Switching is performed with one instruction as the minimum unit of switching, and execution and switching are sequentially performed from task 1 to task n, execution of the task whose desired number of executions has been completed is stopped, and switching of one instruction is performed by the remaining tasks. Execution / switching is performed as a unit, and the cycle until all tasks complete the desired number of executions is defined as one cycle. And performing set according to a ratio of the instruction execution count for each task the number of executions of requests for each task was set in the register.

An arithmetic processing unit according to the present invention is an arithmetic processing unit that executes n tasks in parallel by switching and executing the n tasks in a time-sharing manner by a hardware-controlled swap function. The number of instruction executions is arbitrarily set in a programmable manner, the n counters counting the number of instruction executions of the n tasks, a wait flag circuit for setting a flag indicating a task not to be operated, The next task to be executed is determined based on the task being executed, the information of the wait flag in the wait flag circuit, and the overflow signal of the n counters. A swap control circuit for switching tasks in units of instruction execution; The control circuit executes and switches the n tasks sequentially from task 1 to task n using one instruction as a minimum unit of switching, and stops the execution of the task after the desired number of executions. In the remaining tasks, execution / switching is performed with one instruction as a minimum unit of switching, and one cycle is defined as the time until all tasks finish the desired number of executions, and the number of executions of each task within the one cycle is registered. The setting is performed in accordance with the ratio of the number of instruction executions for each task set in (1).

[Action]

According to the present invention, by using software, the ratio of the number of instruction executions for each task is specified in a register or set in a counter, thereby switching tasks in units of one instruction according to the ratio of the number of instruction executions for each task. Is performed. As a result, by appropriately setting the ratio of the number of instruction executions for each task in accordance with the processing amount of each task and the degree of priority of the processing, the processing of each task can be performed even when a particular task only needs to be given priority. It is possible to perform the processing uniformly and to maintain the real-time property of the parallel processing.

In addition, within one cycle, one instruction is the minimum unit of switching, and execution and switching are sequentially performed from task 1 to task n, execution of the task whose desired number of executions has been completed is stopped, and one instruction is executed for the remaining tasks. By executing / switching as the minimum unit of switching, parallel processing of each task is realized, so that even within one cycle, processing of each task can be performed uniformly and real-time property is maintained. And increase the reaction speed when there is an interruption for each task.

〔Example〕

An embodiment of an arithmetic processing method and an arithmetic processing device according to the present invention will be described with reference to FIGS. 1, 4, and 5. FIG.

In order to solve the problem of the above proposed example and to accept interrupts quickly with low waiting time, even in one cycle, tasks A, B, C, and D are uniformly executed.
Need to switch. Therefore, in the arithmetic processing method of this embodiment, execution / switching of each task A, B, C, D is performed using one instruction as a minimum unit of switching, and the counter 3 shown in FIG.
6 to 6 are waited from the task for which the desired number of executions set according to the instruction execution ratio has been completed, and the same execution and switching are performed for the remaining tasks. Swap to complete the execution of the cycle.

FIG. 4 shows the one-cycle swap shown in FIG.
FIG. 9 is a timing chart of one-cycle swap when execution / switching is performed by the above method.

Considering the reaction speed of the interrupt when the swap as shown in FIG. 4 is performed, the slowest timing is when the interrupt request of the task D occurs after the end of the second execution of the task D at the time 8 on the vertical axis. However, it is 14 instructions until the execution of task D at time 4 of the next cycle.
It is clear that this is an improvement over the 16 instructions in the case of FIG.

FIG. 6 shows the count values of the counters 3 to 6 of each task when the swap is performed at the timing shown in FIG. 4 and the overflows thereof. Symbols A, B, C, and D correspond to each task, respectively. doing.

As a circuit configuration for performing the swap as described above, the block control is not limited to the configuration of FIG. The difference is that the current task is a logic circuit that determines the next task based on the information of the wait flag in the wait circuit 1 and the overflow signals of the counters 3 to 6.

In this way, even when swapping between tasks in one cycle when the execution ratio is taken into account, by switching for each instruction, tasks can be processed uniformly and real-time performance can be maintained. Speed can be increased.

〔The invention's effect〕

According to the present invention, for n tasks to be processed in parallel, the ratio of the instruction execution count is set arbitrarily for each task, and each task is executed, so that a specific task must be processed preferentially. Even when it is necessary, the real-time property can be maintained without losing the uniformity of each task.

In addition, since the execution of each task within one cycle is also distributed, the real-time property can be maintained without losing the uniformity of each task even within one cycle, and the reaction speed of an interrupt can be improved. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an arithmetic processing unit in the proposed example, FIG. 2 is a timing chart showing the timing of task switching in the proposed example in FIG. 1, and FIG. 3 is an overall diagram in the proposed example in FIG. Execution timing diagram, FIG. 4 is a timing diagram of task switching of the arithmetic processing unit in the embodiment of the present invention, FIG. 5 is a timing diagram in which the task switching timing in the embodiment is drawn according to the method of the proposed example,
FIG. 6 is a timing chart showing an example of the timing of a counter in the arithmetic processing unit of FIG. 1, FIG. 7 is a block diagram showing the configuration of a conventional example of the arithmetic processing unit, and FIG. 9 is a timing chart showing the timing of task switching, and FIG. 9 is an overall execution timing chart. 1 ... Wait flag circuit, 2 ... Swap control circuit, 3,4,5,6 ... Counter

Claims (2)

(57) [Claims] 1. A hardware-controlled swap function for n
A task processing method in which the n tasks are executed in parallel by switching and executing the tasks in a time-division manner, wherein the ratio of the number of instruction executions for each task is arbitrarily programmable by a register. The task switching is performed in units of one instruction execution according to the ratio of the number of instruction executions for each task, and the execution / switching of the n tasks is performed using task 1 as the minimum unit of switching. n, execute and switch sequentially, stop the execution of the task for which the desired number of executions has been completed, execute and switch the remaining tasks with one instruction as the minimum unit of switching, and execute the desired number of executions for all tasks. One cycle is defined as the end
An arithmetic processing method, wherein a desired number of executions of each task in one cycle is set according to a ratio of the number of instruction executions for each task set in a register. 2. A hardware controlled swap function for n
An arithmetic processing device that executes the n tasks in parallel by switching and executing the tasks in a time-division manner, wherein the ratio of the number of instruction executions is arbitrarily programmable for each task, n counters for counting the number of instruction executions of n tasks, a wait flag circuit for setting a flag indicating a task not to be operated, information on a task currently being executed, wait flag information in the wait flag circuit, and n A swap control circuit that switches tasks in units of one instruction execution in accordance with the ratio of the number of instruction executions for each task by determining a task to be executed next based on the overflow signals of the counters, The swap control circuit executes and switches the n tasks by one. Are executed and switched sequentially from task 1 to task n as the minimum unit of switching, execution of the task after the desired number of executions is stopped, and execution of one instruction is performed as the minimum unit of switching in the remaining tasks. Switching is performed, and the cycle until all tasks complete the desired number of executions is defined as one cycle. The desired number of executions of each task in the one cycle is set according to the ratio of the number of instruction executions for each task set in the register. An arithmetic processing device characterized by the above.