JPH0528092A - Microprocessor - Google Patents

Abstract

PURPOSE:To provide a microprocessor where the chip size of a CPU core is small and quick context switching is possible independently of the number of nestings by providing the processor with a DMA controller for general register file and plural general register files. CONSTITUTION:A DMA transfer function for each of plural register files 2 and 3 is provided, and register files 2 and 3 are switched at the time of the occurrence of context switching. Or data is shifted to restore data or temporarily save data, and the processing of context switching is completed, and thereafter, next restored data or temporarily saved data is transferred between a memory 5 and register files 2 and 3 by DMA transfer. Thus, quick context switching is possible, and quickly switching is possible and the chip size of the CPU code is reduced in register files 2 and 3 where the number of nestings is 2 or 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general-purpose register file structure and control method for a microprocessor for an embedded controller.

[0002]

2. Description of the Related Art A conventional microprocessor has a plurality of general-purpose register files, and when the context switch occurs, the general-purpose register is switched to speed up the context switch.

As a publicly known example of a method of constructing a general-purpose register file for a microprocessor, Japanese Patent Laid-Open No. 62-5467 is disclosed.
JP-A-62-154166 can be mentioned.

[0004]

When a plurality of register files are provided and context switching is performed, if more nesting occurs than the register files provided, it takes a lot of processing time to save or restore the register files and a controller with a lot of interrupt processing. In the case of, there was a problem that the performance fell.

Further, if the number of register files is increased, the speed of accessing the register file becomes slower and the amount of hardware increases, so that the CPU core chip size of the processor for the embedded controller becomes large and the machine cycle of the processor is slow.

An object of the present invention is to provide a microprocessor having a small CPU core chip size and capable of high-speed context switching regardless of the number of nesting.

[0007]

A DMA transfer function for each register file of a plurality of register files is provided.
When a context switch occurs, the register file is switched or the data is shifted to restore or temporarily save the data to complete the context switch process, and then the DMA transfer is performed to transfer or temporarily restore the next restored data. Transfer the data saved in the memory between the memory and the register file.

[0008]

Since the data is saved or restored by switching the register file or shifting the data, the data processing of the context switch is completed in one cycle, and high-speed context switching can be performed.

Further, thereafter, by the DMA transfer until the next context switch, the data is saved in the memory or restored from the memory to the register file. Therefore, even if the nesting number is at most 2-3 register files, the high speed operation can be achieved. Since context switching is possible, the chip size of the CPU core can be made small, and since the scale of the register file is small, high-speed access is possible, so that the machine cycle of the processor can be made fast.

[0010]

FIG. 1 shows an embodiment of the present invention. As shown in FIG. 1, it is composed of an arithmetic unit 1, a register file 2, a register file 3, a register file switching and DMA control circuit 4, and a RAM 5. The arithmetic unit 1, the register files 2 and 3 are source 1 bus 11, source 2 bus 12 and destination bus 13, and register files 2 and 3 and RAM 5 are connected by memory bus 14. Operand data 2 when performing general register-to-register operation
1 and the register switching data from the general purpose register designation data 22 are output from the DMA control circuit 4 to the source 1 bus 11, the source 2 bus 12, and the destination bus 13 to access the register file.
Thereby, the register file switching and DMA control circuit 4 specifies the register file used by the arithmetic unit. If a context switch occurs when the register file 2 is used in the arithmetic unit 1, the general-purpose register designation data is changed, and the register file accessed in the next operation is switched to the register file 3. When this switching is completed, the DMA transfer of the register file 2 is started, and the register file 2 and RA are used when the processor is not using the memory bus 14 so as not to delay the processing of the processor.
Register file switching and DMA transfer between M5
The control circuit 4 performs this. If DMA transfer of the switching register is being performed at the time of register switching, if there is a DMA transfer in the same direction as the register switching process, wait until the DMA transfer is completed, and cancel the DMA transfer in the reverse direction because it is unnecessary. . The flow of these operations is shown in FIG.

The register file is provided with buses 15 and 16 for shifting data as shown in FIG. 2 and has a configuration for shifting at the time of switching. The configuration shown in FIG. 1 is for switching context switches of local registers. 2 is used to save the global register to the stack pointer.

Further, when there are two or more register files, there is a register file to be switched even if the DMA transfer is not completed until the next context switch.
Switching is possible, and it is effective because switching is performed in one cycle until the entire register file is used.

[0013]

According to the present invention, even if the number of register files is small, high-speed context switching can be performed for many nesting, and the CPU core chip size can be reduced.

Further, since the size of the register file is small, the register file can be accessed at high speed and the machine cycle can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a calculation unit of the present invention.

FIG. 2 is a configuration diagram of a register file of the present invention.

FIG. 3 is an operation flow chart of the present invention.

[Explanation of symbols]

1 ... arithmetic unit, 2 ... register file, 3 ... register file, 4 ... Register file switching and DMA control circuit, 5 ... RAM, 11 ... Source 1 bus, 12 ... Source 2 bus, 13 ... destination bus 14 ... Memory bus, 15 ... shift bus, 16 ... shift bus, 21 ... Operand data, 22 ... General-purpose register designation data.

Claims (5)

[Claims] 1. A processor is provided with a general-purpose register file DMA controller and a plurality of general-purpose register files.
At the time of switching the processing of the processor, the plurality of general purpose register files to be used are switched to save or restore the data, and the data of the plurality of general purpose register files are stored in the memory by the general purpose register file DMA controller during the processing after the switching. A microprocessor characterized by being saved in or restored from. 2. A general-purpose register file DMA controller and a plurality of general-purpose register files are provided, the plurality of general-purpose register files are configured so that data can be shifted between the general-purpose register files, and at the time of switching the processing of the processor, the general-purpose register files are general-purpose. A micro characterized in that data in a register file is shifted to save or restore the data, and data in a plurality of general-purpose register files is saved or restored in a memory by the DMA controller for general-purpose register file during processing after switching. Processor. 3. The microprocessor according to claim 1, wherein each of the register files of the plurality of general purpose register files is provided with a data save DMA transfer completion flag and a data restore DMA transfer flag, and is a general purpose switch target when saving data. The data saving completion flag of the register file is checked, the data restoration DMA transfer completion flag of the general purpose register file to be switched is checked at the time of data restoration, and the processor is stopped until the DMA transfer is completed and each flag is set. And a microprocessor. 4. A DMA controller for a general-purpose register file, wherein the bus controller has a lower priority than the bus use right. 5. A DMA controller for a general-purpose register file, wherein a data transfer bus different from a memory bus of a processor is provided to perform DMA transfer.
controller.