JPS63223841A - Measuring system for program including rate - Google Patents

Abstract

PURPOSE:To accurately grasp the degree of evaluation of a program to be evaluated by measuring the ratio of the executed instruction number as a program including rate. CONSTITUTION:An input interpretation instructing part 2 delivers an instruction to set a branch instruction interrupting mode by a setting instruction of said interrupting mode supplied from an input device 1 and also delivers an indication for calculation of the program including rate after interpreting a range on a main memory for an evaluation subject program 5 supplied from the device 1 and the undergo the measurement of said including rate. An including rate calculating part 9 calculates the ratio of the executed instructions in a range informed when an instruction is received from the part 2 for calculation of the program including rate and outputs the result of calculation to an output device 10 after editing. An instruction word interpreting part 8 informs all instruction addresses of the program 5 to the part 9 by an instruction of the part 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring program coverage in an information processing system, and particularly to a method for measuring the ratio of instructions executed at least once in a program to be evaluated.

[Prior art] When a program is newly developed, it is necessary to evaluate the program using test data, etc., in order to confirm whether the program achieves its intended purpose. It will be done.

Normally, in evaluating this program, the person in charge of evaluation considers several evaluation items in advance to cover all instructions in the program to be evaluated, conducts tests on these evaluation items, and finds results that are satisfactory in all evaluation items. When this was obtained, the evaluation was considered complete.

[Problem that the invention seeks to solve]

However, it is extremely difficult to list evaluation items that cover all instructions in the program to be evaluated.
Therefore, there is a problem in that it cannot be said that the evaluation of the program to be evaluated is complete just because all the evaluation items considered in advance are satisfied.

The present invention has been made in view of these circumstances.
The purpose of this is to provide a method for measuring the ratio of instructions executed at least once during the evaluation of a program to be evaluated, thereby making it possible to accurately determine the degree of evaluation of the program to be evaluated. .

[Means for solving problems]

In order to achieve the above object, the present invention executes a branch instruction in a program in response to the setting of a branch instruction interrupt mode, so that at least a pre-branch address and a post-branch address are generated before the first instruction after the branch is executed. In a computer system having a branch instruction interrupt mechanism that generates an internal interrupt by notifying the branch instruction interrupt mechanism, a pre-branch address activated by an internal interrupt by the branch instruction interrupt mechanism and currently notified from the branch instruction interrupt mechanism; The range indicated by the post-branch address stored in the post-branch address storage unit at the previous startup is stored as executed instruction area information in the executed instruction area information storage unit, and the post-branch address notified this time is stored as executed instruction area information. branch instruction interrupt processing means for storing in the address storage means; instruction word address notification means for notifying the addresses of all instruction words within the address range of the program to be evaluated; a coverage rate calculation means for calculating a ratio of executed instructions as a program coverage rate based on the address and executed instruction area information stored in the executed instruction area information storage means; and a coverage rate calculation means calculated by the coverage rate calculation means. and an output means for outputting the program coverage rate obtained.

[Effect]

When a branch instruction of the program to be evaluated is executed, the branch instruction interrupt mechanism notifies the pre-branch address and the post-branch address, generates an internal interrupt, and activates the branch instruction interrupt processing means.

When the branch instruction interrupt processing means is activated, it has executed the range indicated by the pre-branch address notified this time by the branch instruction interrupt mechanism and the post-branch address stored in the post-branch address storage means at the time of previous activation. It is stored as instruction area information in the executed instruction area information storage means, and the currently notified post-branch address is stored in the post-branch address storage means. Such processing is performed every time a branch instruction in the program to be evaluated is executed, and as a result, at the end of execution of the program to be evaluated, information regarding the area of executed instructions out of all address areas of the program to be evaluated is It will be stored in the completed instruction area information storage means.

Thereafter, the coverage rate calculation means calculates the executed instructions based on the addresses of all instruction words obtained from the instruction word address notification means and the executed instruction θ area information stored in the executed instruction area information storage means. The ratio is calculated as the program coverage rate, and is output from the output means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which the input value W
An instruction to set the branch instruction interrupt mode is given by the setting instruction of the branch instruction v1 included mode inputted from L1, and also manually inputted from the input device 1! an input interpretation instruction unit 2 that interprets a range (for example, given by a start address and an end address) on the main memory of the evaluation target program 5 that is the target of the in rate measurement and gives an instruction to calculate the coverage rate;
A known branch instruction interrupt mechanism 3 that notifies a pre-branch address and a post-branch address and generates a branch instruction interrupt, which is an internal interrupt, by executing a branch instruction in the evaluation target program 5; a branch instruction interrupt processing unit 4 that operates when interrupted by a branch instruction interrupt processing unit 4; a post-branch address storage unit 7 in which a post-branch address (branch destination address of a branch instruction) is stored by the branch instruction interrupt processing unit 4; A coverage rate calculation unit 9 that calculates the ratio of executed instructions in the notified range when receiving an instruction to calculate the coverage rate from the instruction unit 2, and edits and outputs the calculation result to the output device 10; an instruction word interpretation unit 8 that notifies the coverage rate calculation unit 9 of the addresses of all instructions of the evaluation target program 5 according to instructions;
It includes an executed instruction area information storage unit 6 in which execution method instruction storage area information is stored by the branch instruction interrupt processing unit 4 and referenced by the coverage rate calculation unit 9.

FIG. 2 is a diagram illustrating the operation when writing executed instruction area information in the executed instruction area information storage section 6, using the routine from address PO to address P4 of the evaluation target program 5 as an example.

In evaluation target program 5, address PO.

PI, P2. P3. P4 is the branch destination address of the branch instruction (
address after branch), and address Bl.

B2. B3. B4 is the address of the branch instruction itself. First, when a branch instruction that branches to address PO of the evaluation target program 5 is executed, a branch instruction interrupt is generated by the branch instruction interrupt mechanism 3, and the branch instruction interrupt processing section 4 operates. The branch instruction interrupt processing unit 4 stores the post-branch address PO notified from the branch instruction interrupt mechanism 3 in the post-branch address storage unit 7.
(Here, a description of the procedure for storing executed instruction area information before branching to address PO is omitted.)

Next, when a branch instruction at address B1 of the evaluation target program 5 is executed and a branch instruction interrupt occurs at address P1, which is the branch destination, the branch instruction interrupt processing unit 4 is notified from the branch instruction interrupt mechanism 3. The range between the pre-branch address Bl and the address PO stored in the post-branch address storage unit 7 at this time (range from address PO to address B1) is stored as executed instruction area information M1 in the executed instruction area information storage unit 6. After that, the post-branch address P1 notified together with the pre-branch address B1 is stored in the post-branch address storage unit 7.
to be memorized. Similarly, address B2°B3. By executing the branch instruction of B4, addresses P2. P3. P4
A branch instruction interrupt occurs in M2., and the branch instruction interrupt processing unit 4 records the executed instruction area information M2. M3. M4 is stored in the executed instruction area information storage section 6.

FIG. 3 is a diagram showing an example of the stored contents of the executed instruction area information storage section 6. As shown in FIG. The executed instruction area information storage unit 6 of this embodiment has bits that correspond one-to-one with each address of the main memory. For example, the bit with bit number O is stored at address 0 on the main memory, The bit corresponds to address 100 on the main memory.

Then, the bit of the bit number corresponding to the address of the executed instruction is turned on, and the bit corresponding to the address of the unexecuted instruction is turned off. For example, if the start address of the program to be evaluated 5 on the main memory is address S and the end address is address E, the executed instruction area information of the program to be evaluated 5 is stored in the executed instruction area information storage unit 6 in FIG. is stored in the storage area 61 in the range from bit number S to bit number E. Executed instruction il area information storage area 6
1 includes executed instruction area information Ml shown in the explanation of FIG.
, M2. M3. M4 exists, and executed instruction area information Ml, M2 . M3. All focuses included in M4 are on. Similarly, in the executed instruction area M1111 storage area 61, the bit corresponding to the executed instruction area of the evaluation target program 5 is the executed instruction area information M1, M2.
．． M3. Like M4, it is on, and the other bits, ie, the pinot l- corresponding to the unexecuted instruction area of the evaluation target program 5, are off.

Now, after the execution of the evaluation target program 5 is completed, the coverage rate calculation unit 9, which has been notified by the input interpretation instruction unit 2 of the start address S and end address E of the evaluation target program 5, which are the coverage rate calculation range, uses the instruction word The interpreter 8 is instructed to report the addresses of all instruction words from address S to address E. In response to this, the command interpreter 8 calculates the addresses of all commands from address S to address E! il ratio calculation part 9
Reports will be made one by one. Thereafter, the coverage calculation unit 9 outputs the address of the instruction word sequentially reported by the instruction word interpretation unit 8 to the output device 10, but at this time, the executed instruction area corresponding to the address of the reported instruction word is It is determined whether the bit in the information storage area 61 is on or not, and if it is on, an identification word indicating that it is the address of the execution method instruction word is added to the address to be outputted above and edited and output, and when it is off. If there is, for example, only the address of the instruction word is output.

Further, the coverage calculation unit 9 counts the number of instructions successively reported by the instruction interpretation unit 8, and turns on the bit of the executed instruction frequency information storage area 61 corresponding to the address of the reported instruction word. In other words, the number of execution command words is counted, and finally the ratio of the number of execution command words to the total number of command words (this ratio is calculated as a percentage by dividing the number of execution command words by the total number of command words). (or simply in the form of "number of executed instruction words/total number of instruction words"), and this calculation result is outputted to the output device 10 as the program coverage rate for the evaluation target program 5.
Output to.

In addition, in the above embodiment, in addition to outputting the ratio of the number of execution method instruction words to the total number of instruction words as the program coverage rate, a format that allows it to be determined whether the address of an executed instruction or an address of an unexecuted instruction is used. Address information was also output in , but in systems where you simply want to know the ratio of the number of execution method instructions, outputting the address can be omitted.

〔Effect of the invention〕

As explained above, the present invention uses branch instruction interrupts to sequentially store executed instruction area information during the execution process of the evaluation target program, and after the execution of the evaluation target program is finished, the stored execution method area information is stored. Based on this, the ratio of executed instructions of the program to be evaluated is calculated, and the ratio of the number of executed instructions can be measured as the program coverage rate without any modification to the program to be evaluated. Can be done. Therefore, it is possible to accurately grasp the evaluation level of the program to be evaluated.

In addition to outputting the ratio of the number of executable instructions in the program to be evaluated, it also distinguishes and outputs the addresses of executed instructions and the addresses of unexecuted instructions, so that it is possible to determine which instructions in the program to be evaluated are the unexecuted instructions. It becomes easy to determine whether the program is executed, and in the next evaluation step, evaluation can be performed focusing on unexecuted instructions, which has the effect of efficiently improving the degree of evaluation of the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation when storing executed instruction area information in the executed instruction area information storage unit 6, and FIG. 3 is an explanatory diagram of executed instruction area information. FIG. 6 is a diagram showing an example of storage contents of a storage unit 6. FIG. In the figure, 1... input device, 2... input interpretation instruction unit, 3... branch instruction interrupt mechanism, 4... branch instruction interrupt processing unit, 5... program to be evaluated, 6... ... Executed instruction area information storage section, 7... Post-branch address storage section,
8... Instruction word interpretation section, 9... Coverage rate calculation section, 10.
...Output device. Patent distributor NEC Corporation

Claims (2)

[Claims] (1) In response to the branch instruction interrupt mode setting, by executing a branch instruction in the program, at least the pre-branch address and post-branch address are notified and an internal interrupt is generated before the first instruction after the branch is executed. In a computer system having a branch instruction interrupt mechanism that generates a branch instruction interrupt mechanism, a pre-branch address that is activated by an internal interrupt by the branch instruction interrupt mechanism and that is notified this time from the branch instruction interrupt mechanism and a post-branch address stored at the previous activation. A branching instruction that stores a range indicated by the post-branch address stored in the means in the executed instruction area information storage means as executed instruction area information, and stores the currently notified post-branch address in the post-branch address storage means. an interrupt processing means, an instruction word address notifying means for notifying the addresses of all the instructions within the address range of the evaluation target program, the addresses of all the instructions obtained from the instruction word address notifying means, and the executed instruction area. Coverage rate calculation means for calculating the ratio of executed instructions as a program coverage rate based on the executed instruction area information stored in the information storage means; and outputting the program coverage rate calculated by the coverage rate calculation means. A program coverage measurement method characterized by comprising: an output means. (2) In the program coverage measurement method according to claim 1, the coverage calculation means includes, together with the program coverage,
A method for measuring program coverage rate, characterized in that the address of the executed instruction is outputted from the output means while being distinguished from the address of an unexecuted instruction.