JPS61170845A - Checking system of rom for sequence control - Google Patents

Checking system of rom for sequence control

Info

Publication number
JPS61170845A
JPS61170845A JP1216885A JP1216885A JPS61170845A JP S61170845 A JPS61170845 A JP S61170845A JP 1216885 A JP1216885 A JP 1216885A JP 1216885 A JP1216885 A JP 1216885A JP S61170845 A JPS61170845 A JP S61170845A
Authority
JP
Japan
Prior art keywords
rom
control
check
block
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1216885A
Other languages
Japanese (ja)
Inventor
Toru Ichiki
徹 市木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1216885A priority Critical patent/JPS61170845A/en
Publication of JPS61170845A publication Critical patent/JPS61170845A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To check the outline of the operation of a ROM by dividing the memory area of the ROM into two blocks and storing check data in the second block. CONSTITUTION:Control data is stored in a part I of the memory area of a ROM1 of the test object, and check data is stored in a part II. When control is requested, an address signal A from an external controller is inputted to the ROM1 through a selector 2, and a prescribed control output is sent through a gate 4. Unless control is requested, the ROM1 is checked. In this check, the address input of the ROM1 is inputted to the ROM1 through the selector 2, and corresponding output data stored in the part II is sent back and inputted to the selector 2 through a flip flop 3. SInce the time required for the completion of the series of operations is a certain value at the normal operation time, this time is monitored by a counter to discriminate whether the operation is normal or abnormal.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は制御装置の自己監視方式に係り、特にシーケン
ス制御用ROMのチェックをROM停止中に行うシーケ
ンス制御用ROMチェック方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a self-monitoring method for a control device, and particularly to a sequence control ROM check method in which a sequence control ROM is checked while the ROM is stopped.

従来のROMチェック方式はかなりの周辺装置を使用し
て行っているので規模が大きくチェックの実施が大変で
あるので此れを改善出来るチェック方式の開発が望まれ
ていた。
Since the conventional ROM check method uses a large number of peripheral devices, the scale of the check is large and it is difficult to carry out the check.Therefore, it has been desired to develop a check method that can improve this problem.

〔従来の技術〕[Conventional technology]

従来のROMチェック方式はシステム的に成る周期で擬
似動作を行ってROMを含めて全体的なチェックを行う
方式と、シーケンス制御部に擬似コマンドを送出し、其
の応答を判定して装置の動作をチェックする方式があっ
た。
Conventional ROM check methods include one in which a pseudo operation is performed at systematic intervals to check the entire system including the ROM, and the other is a method in which a pseudo command is sent to the sequence control unit and the response is judged to determine the operation of the device. There was a way to check.

何れの方式もチェックの為に必要な装置類が大きくなり
、而もチェック動作に時間がかかり過ぎると云う欠点が
あった。
Both methods have the disadvantage that the equipment required for the check is large and the check operation takes too much time.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は上記従来方式の欠点を除去し、より簡便
に出来、且つROMの動作の略概要をチェック出来るシ
ーケンス制御用ROMチェック方弐を提供することであ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a sequence control ROM check method which eliminates the drawbacks of the above-mentioned conventional methods, is simpler, and allows a general outline of the ROM operation to be checked.

〔問題点を解決するための手段〕[Means for solving problems]

問題点を解決するための手段は、ROMのメモリエリア
を二つのブロックに分け、第一ブロックに制御用データ
を格納し、第二ブロックに81゜Mチェック用データを
格納し、該ROMが制御用として使用される時は前記第
一ブロックの該制御用データを使用し、8g ROMが
制御用として使用されていない時は前記第二ブロックの
該ROMチェック用データを使用し、前記第二ブロック
の第一アドレスには前記第二ブロックの第二アドレスを
記入し、以下前記第二ブロックの最終アドレスには前記
第二ブロックの第一アドレスを記入することにより順次
前記第二ブロックの全アドレスの格納内容をチェックす
ることにより達成される。
The means to solve the problem is to divide the ROM memory area into two blocks, store control data in the first block, store 81°M check data in the second block, and store the 81°M check data in the second block. When the 8g ROM is not used for control, the control data of the first block is used, and when the 8g ROM is not used for control, the ROM check data of the second block is used. The second address of the second block is written in the first address of the second block, and the first address of the second block is written in the final address of the second block, thereby sequentially writing all the addresses of the second block. This is achieved by checking the stored contents.

〔作用〕 本発明に依ると問題点を解決するための手段の項で述べ
た様にROMの第二ブロックの全アドレスのデータを自
動的に読み出しを行い、其の間の動作の良否を判定出来
ると云う効果が生まれる。
[Operation] According to the present invention, as described in the section of means for solving the problems, data at all addresses in the second block of the ROM is automatically read out, and the quality of the operation during that time is determined. It produces the effect that it can be done.

〔実施例〕〔Example〕

図は本発明に依るシーケンス制御用ROMチェック方式
の一実施例を示す図である。
The figure is a diagram showing an embodiment of a sequence control ROM check method according to the present invention.

図中、1はROM、2はセレクタ、3はフリ・ノブフロ
ップ、4はゲート、5はデータ検出器、6はカウンタで
ある。
In the figure, 1 is a ROM, 2 is a selector, 3 is a free-knob flop, 4 is a gate, 5 is a data detector, and 6 is a counter.

以下図に従って本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

ROMIは試験対象となっているROMであり、其のメ
モリエリアの内Iの部分に制御用データを、■の部分に
チェック用データを夫々記入しておく。
ROMI is a ROM to be tested, and in its memory area, control data is written in the I part, and check data is written in the part ■.

制御要求が有る場合には、外部の制御装置から送られて
来るアドレス信号はルートAを通りセレクタ2を介して
ROMIに入る。此の結果該アドレスに対応するROM
Iに記憶されているデータ(ROMIのIの部分に格納
されている)はゲート4を通って出力されて所定の制御
動作を行う。
When there is a control request, an address signal sent from an external control device passes through route A and enters ROMI via selector 2. As a result, the ROM corresponding to the address
The data stored in I (stored in the I portion of ROMI) is output through gate 4 to perform a predetermined control operation.

又制御0要求”′出7パ4°゛場合′″2!・1発明′
″     −依るとROMのチェックを行う。即ち、
ROMIのアドレス入力はルートBを通りセレクタ2に
よりROMIに入り、ROMIの■の部分に記憶されて
いる其のアドレスに対応する出力データはフリップフロ
ップ3を介して折り返され、ルートBを通りセレクタ2
に入力される。南北の時ゲート4は閉じており、従って
制御出力が外部に出ることはない。
Also, if control 0 request "'output 7 pa 4°'"2!・1 invention'
” - Checks the ROM accordingly, i.e.
The address input of ROMI passes through route B and enters ROMI by selector 2, and the output data corresponding to that address stored in the part marked with ROMI is looped back via flip-flop 3, passes through route B, and enters selector 2.
is input. The gate 4 is closed when the direction is north/south, so the control output does not go outside.

制御の要求が出ていない時、ROMIの■の部分の最初
のアドレスaを指定する。此の結果アドレスaに書込ま
れているデータがフリップフロップ3に人力される。此
のアドレスaに書込まれているデータはアドレスaの次
のアドレスbである。
When no control request is issued, specify the first address a in the part marked with ``■'' in the ROMI. As a result, the data written to address a is manually input to flip-flop 3. The data written to this address a is the next address b after address a.

従って次はアドレスbが指定され、此の結果アドレスb
に書込まれているデータがフリップフロップ3に人力さ
れる。此のアドレスbに書込まれているデータはアドレ
スbの次のアドレスCである。
Therefore, address b is specified next, and as a result, address b
The data written in is manually input to the flip-flop 3. The data written to this address b is the next address C after address b.

従って次はアドレスCが指定され、以下同じ手順でRO
MIの■の部分を順次読取る。
Therefore, address C is specified next, and the same procedure is followed for RO.
Read the ■ part of MI sequentially.

上記一連の動作が完了するのに要する時間は、正常動作
の場合には成る一定値を取るので、カウンタ6は此の時
間を監視し、所定の時間で終了した時は正常、此れ以外
の場合は異常であると判定する。
The time required for the above series of operations to complete takes a constant value in the case of normal operation, so the counter 6 monitors this time, and when it completes within a predetermined time, it is considered normal and other than this. If so, it is determined that there is an abnormality.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に本発明によれば、極めて簡単な
回路を付加することによりROMの動作の略概要をチェ
ック出来ると云う大きい効果がある。
As described in detail above, the present invention has the great effect of being able to check the general outline of the operation of the ROM by adding an extremely simple circuit.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明に依るシーケンス制御用ROMチェック方式
の一実施例を示す図である。 図中、lはROM、2はセレクタ、3はフリップフロッ
プ、4はゲート、5はデータ検出器、6はカウンタであ
る。 1余辷り
The figure is a diagram showing an embodiment of a sequence control ROM check method according to the present invention. In the figure, l is a ROM, 2 is a selector, 3 is a flip-flop, 4 is a gate, 5 is a data detector, and 6 is a counter. 1 overstepping

Claims (1)

【特許請求の範囲】[Claims] ROMのメモリエリアを二つのブロックに分け、第一ブ
ロックに制御用データを格納し、第二ブロックに該RO
Mチェック用データを格納し、該ROMが制御用として
使用される時は前記第一ブロックの該制御用データを使
用し、該ROMが制御用として使用されていない時は前
記第二ブロックの該ROMチェック用データを使用し、
前記第二ブロックの第一アドレスには前記第二ブロック
の第二アドレスを記入し、以下前記第二ブロックの最終
アドレスには前記第二ブロックの第一アドレスを記入す
ることにより順次前記第二ブロックの全アドレスの格納
内容をチェックすることを特徴とするシーケンス制御用
ROMチェック方式。
The ROM memory area is divided into two blocks, the first block stores control data, and the second block stores the RO.
M check data is stored, and when the ROM is used for control, the control data of the first block is used, and when the ROM is not used for control, the control data of the second block is used. Using the ROM check data,
The second address of the second block is written in the first address of the second block, and the first address of the second block is written in the final address of the second block. A sequence control ROM check method characterized by checking the stored contents of all addresses.
JP1216885A 1985-01-25 1985-01-25 Checking system of rom for sequence control Pending JPS61170845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1216885A JPS61170845A (en) 1985-01-25 1985-01-25 Checking system of rom for sequence control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1216885A JPS61170845A (en) 1985-01-25 1985-01-25 Checking system of rom for sequence control

Publications (1)

Publication Number Publication Date
JPS61170845A true JPS61170845A (en) 1986-08-01

Family

ID=11797904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1216885A Pending JPS61170845A (en) 1985-01-25 1985-01-25 Checking system of rom for sequence control

Country Status (1)

Country Link
JP (1) JPS61170845A (en)

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