JP7756786B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法Info
- Publication number
- JP7756786B2 JP7756786B2 JP2024506109A JP2024506109A JP7756786B2 JP 7756786 B2 JP7756786 B2 JP 7756786B2 JP 2024506109 A JP2024506109 A JP 2024506109A JP 2024506109 A JP2024506109 A JP 2024506109A JP 7756786 B2 JP7756786 B2 JP 7756786B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- semiconductor
- step portion
- bonding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
- H10W70/424—Cross-sectional shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022038352 | 2022-03-11 | ||
| JP2022038352 | 2022-03-11 | ||
| PCT/JP2023/007647 WO2023171505A1 (ja) | 2022-03-11 | 2023-03-01 | 半導体装置及び半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2023171505A1 JPWO2023171505A1 (https=) | 2023-09-14 |
| JPWO2023171505A5 JPWO2023171505A5 (https=) | 2024-10-15 |
| JP7756786B2 true JP7756786B2 (ja) | 2025-10-20 |
Family
ID=87935277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024506109A Active JP7756786B2 (ja) | 2022-03-11 | 2023-03-01 | 半導体装置及び半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20250149413A1 (https=) |
| JP (1) | JP7756786B2 (https=) |
| CN (1) | CN118830068A (https=) |
| DE (1) | DE112023001343T5 (https=) |
| WO (1) | WO2023171505A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2025182086A1 (https=) * | 2024-03-01 | 2025-09-04 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009500841A (ja) | 2005-07-08 | 2009-01-08 | エヌエックスピー ビー ヴィ | 半導体デバイス |
| JP2017108192A (ja) | 2017-03-24 | 2017-06-15 | 三菱電機株式会社 | 半導体装置 |
| JP2021150548A (ja) | 2020-03-23 | 2021-09-27 | 富士電機株式会社 | 半導体製造装置及び半導体装置の製造方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5112972B2 (ja) * | 2008-06-30 | 2013-01-09 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置およびその製造方法 |
| JP5745238B2 (ja) * | 2010-07-30 | 2015-07-08 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置およびその製造方法 |
| JP7351134B2 (ja) * | 2019-08-08 | 2023-09-27 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
| JP7494521B2 (ja) | 2020-03-30 | 2024-06-04 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
-
2023
- 2023-03-01 US US18/838,311 patent/US20250149413A1/en active Pending
- 2023-03-01 JP JP2024506109A patent/JP7756786B2/ja active Active
- 2023-03-01 DE DE112023001343.8T patent/DE112023001343T5/de active Pending
- 2023-03-01 WO PCT/JP2023/007647 patent/WO2023171505A1/ja not_active Ceased
- 2023-03-01 CN CN202380025667.4A patent/CN118830068A/zh active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009500841A (ja) | 2005-07-08 | 2009-01-08 | エヌエックスピー ビー ヴィ | 半導体デバイス |
| JP2017108192A (ja) | 2017-03-24 | 2017-06-15 | 三菱電機株式会社 | 半導体装置 |
| JP2021150548A (ja) | 2020-03-23 | 2021-09-27 | 富士電機株式会社 | 半導体製造装置及び半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE112023001343T5 (de) | 2024-12-19 |
| US20250149413A1 (en) | 2025-05-08 |
| JPWO2023171505A1 (https=) | 2023-09-14 |
| WO2023171505A1 (ja) | 2023-09-14 |
| CN118830068A (zh) | 2024-10-22 |
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