JP4698658B2 - 半導体チップ搭載用の絶縁基板 - Google Patents
半導体チップ搭載用の絶縁基板 Download PDFInfo
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- JP4698658B2 JP4698658B2 JP2007309193A JP2007309193A JP4698658B2 JP 4698658 B2 JP4698658 B2 JP 4698658B2 JP 2007309193 A JP2007309193 A JP 2007309193A JP 2007309193 A JP2007309193 A JP 2007309193A JP 4698658 B2 JP4698658 B2 JP 4698658B2
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1305—Bipolar Junction Transistor [BJT]
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Description
前記多数の搭載部の夫々には、前記搭載部の端よりも内側に後退してなる同一形状の導電パターンを有するとともに、前記多数の搭載部のうちの第1の搭載部の導電パターンと前記第1の搭載部と隣接した前記多数の搭載部のうちの第2の搭載部の導電パターンは、前記第1の搭載部と前記第2の搭載部の間に設けられた連結部により電気的に接続され、裏面には前記導電パターンと電気的に接続され、前記搭載部に対応する領域の端よりも後退して設けられた外部電極を有し、前記連結部により前記導電パターンに電解メッキが施されている事で解決するもので有る。
(B)は第1の絶縁基板22の裏面側に形成した導電パターンを示す平面図である。
斯様に金メッキ層34を形成した共通基板21の各搭載部20毎に、半導体チップ33をダイボンド、ワイヤボンドする。半導体チップ33はアイランド部25表面にAgペーストなどの接着剤によって固定し、半導体チップ33の電極パッドとリード部32a、32bとを各々ワイヤ34で接続する。半導体チップ33としては、バイポーラトランジスタ、パワーMOSFET等の3端子の能動素子を形成している。パワーMOSFETであれば、外部電極31a、31bがドレイン電極となり、外部電極31c、31dが各々ソース電極とゲート電極になる。
共通基板21の上方に移送したディスペンサから所定量のエポキシ系液体樹脂を滴下(ポッティング)し、すべての半導体チップ33を共通の樹脂層35で被覆する。例えば一枚の共通基板21に100個の半導体チップ33を搭載した場合は、100個全ての半導体チップ33を一括して被覆する。前記液体樹脂として例えばCV576AN(松下電工製)を用いた。滴下した液体樹脂は比較的粘性が高く、表面張力を有しているので、その表面が湾曲する。
樹脂層35の湾曲した表面を、平坦面に加工する。加工するには、樹脂が硬化する前に平坦な成形部材を押圧して平坦面に加工する手法と、滴下した樹脂層35を100〜200度、数時間の熱処理(キュア)にて硬化させた後に、湾曲面を研削することによって平坦面に加工する手法とが考えられる。研削にはダイシング装置を用い、ダイシングブレードによって樹脂層35の表面が共通基板21から一定の高さに揃うように、樹脂層35表面を削る。この工程では、樹脂層35の膜厚を0.3〜1.0mmに成形する。平坦面は、少なくとも最も外側に位置する半導体チップ33を個別半導体装置に分離したときに、規格化したパッケージサイズの樹脂外形を構成できるように、その端部まで拡張する。前記ブレードには様々な板厚のものが準備されており、比較的厚めのブレードを用いて、切削を複数回繰り返すことで全体を平坦面に形成する。
次に、搭載部20毎に樹脂層35を切断して各々の半導体装置に分離する。切断にはダイシング装置を用い、ダイシングブレード36によってダイシングライン24に沿って樹脂層35と共通基板21とを同時に切断することにより、搭載部20毎に分割した半導体装置を形成する。ダイシング工程においては共通基板21の裏面側にブルーシート(たとえば、商品名:UVシート、リンテック株式会社製)を貼り付け、前記ダイシングブレードがブルーシートの表面に到達するような切削深さで切断する。この時には、共通基板21の表面にあらかじめ形成した合わせマークをダイシング装置側で自動認識し、これを位置基準として用いてダイシングする。
本発明によれば、リードフレームを用いた半導体装置よりも更に小型化できるパッケージ構造を提供できる利点を有する。このとき、リード端子が突出しない構造であるので、実装したときの占有面積を低減し、高密度実装を実現できる。
Claims (4)
- 大判の共通基板の表面に縦横に並び、同一形状の導電パターンが設けられた矩形の複数の搭載部を有し、前記複数の搭載部に半導体チップを設け、前記半導体チップも含め、前記複数の搭載部を樹脂で一括して封止してなる樹脂層を形成し、その後に、前記複数の搭載部が設けられた前記共通基板および前記樹脂層を含めてダイシングブレードにより切断することにより、前記複数の搭載部を個々の搭載部に分割し、上面、下面および4側面から成るパッケージを形成するための前記共通基板である半導体チップ搭載用の絶縁基板であり、
前記複数の搭載部の夫々の導電パターンは、前記パッケージの端面よりも内側に後退するとともに、
前記多数の搭載部の内の第1の搭載部の導電パターンと前記第1の搭載部と第1の方向に隣接した前記多数の搭載部の内の第2の搭載部の導電パターンは、前記ダイシングブレードが通過するダイシングラインを超え、前記第1の搭載部と前記第2の搭載部の間を通過する第1の連結部により電気的に接続され、
前記第1の連結部と直行する第2の方向に延在され、前記第1の搭載部の導電パターンと前記第1の搭載部と前記第2の方向に隣接した第3の搭載部の導電パターンは、前記ダイシングラインを超えて、前記第1の搭載部と前記第3の搭載部の間を通過する第2の連結部により電気的に接続され、
前記搭載部に対応する前記絶縁基板の裏面には、前記搭載部毎にスルーホールが設けられ、前記第1の連結部、第2の連結部および前記スルーホールを介して前記導電パターンと電気的に接続され、前記パッケージの端面よりも後退して設けられた外部電極を有する事を特徴とした半導体チップ搭載用の絶縁基板。 - 前記導電パターンは、前記半導体チップを搭載する部分であるアイランド部と、前記半導体チップの電極パッドと接続されるリード部を有し、間隔を隔てて前記縦横に並んだ搭載部の間は、ダイシングラインとなる請求項1に記載の半導体チップ搭載用の絶縁基板。
- 前記絶縁基板は、セラミックまたはガラスエポキシから成る請求項1または請求項2に半導体チップ搭載用の絶縁基板。
- 前記絶縁基板には、前記ダイシングラインを形成する際の位置基準となるマークが設けられている請求項1、請求項2または請求項3に記載の半導体チップ搭載用の絶縁基板。
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JP32832098A Division JP4073098B2 (ja) | 1998-11-18 | 1998-11-18 | 半導体装置の製造方法 |
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WO2021006297A1 (ja) * | 2019-07-10 | 2021-01-14 | 株式会社デンソー | 半導体パッケージ、電子装置、および半導体パッケージの製造方法 |
JP7310733B2 (ja) * | 2019-07-10 | 2023-07-19 | 株式会社デンソー | 半導体パッケージ、電子装置、および半導体パッケージの製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08107161A (ja) * | 1994-06-22 | 1996-04-23 | Seiko Epson Corp | 電子部品、電子部品素材および電子部品の製造方法 |
JPH08153819A (ja) * | 1994-11-29 | 1996-06-11 | Citizen Watch Co Ltd | ボールグリッドアレイ型半導体パッケージの製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH08107161A (ja) * | 1994-06-22 | 1996-04-23 | Seiko Epson Corp | 電子部品、電子部品素材および電子部品の製造方法 |
JPH08153819A (ja) * | 1994-11-29 | 1996-06-11 | Citizen Watch Co Ltd | ボールグリッドアレイ型半導体パッケージの製造方法 |
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