JP7724693B2 - クロック伝達回路、撮像素子、及びクロック伝達回路の製造方法 - Google Patents

クロック伝達回路、撮像素子、及びクロック伝達回路の製造方法

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Publication number
JP7724693B2
JP7724693B2 JP2021189281A JP2021189281A JP7724693B2 JP 7724693 B2 JP7724693 B2 JP 7724693B2 JP 2021189281 A JP2021189281 A JP 2021189281A JP 2021189281 A JP2021189281 A JP 2021189281A JP 7724693 B2 JP7724693 B2 JP 7724693B2
Authority
JP
Japan
Prior art keywords
circuit
clock
circuit element
clock signal
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2021189281A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023076093A5 (https=
JP2023076093A (ja
Inventor
英敏 吉村
佑 淨法寺
行信 杉山
陸 米川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hamamatsu Photonics KK
Original Assignee
Hamamatsu Photonics KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2021189281A priority Critical patent/JP7724693B2/ja
Application filed by Hamamatsu Photonics KK filed Critical Hamamatsu Photonics KK
Priority to PCT/JP2022/036575 priority patent/WO2023089964A1/ja
Priority to KR1020247019902A priority patent/KR20240108480A/ko
Priority to DE112022005614.2T priority patent/DE112022005614T5/de
Priority to US18/711,253 priority patent/US12604116B2/en
Priority to GB2408578.9A priority patent/GB2628256A/en
Priority to CN202280076757.1A priority patent/CN118266171A/zh
Priority to TW111141076A priority patent/TW202331808A/zh
Publication of JP2023076093A publication Critical patent/JP2023076093A/ja
Publication of JP2023076093A5 publication Critical patent/JP2023076093A5/ja
Priority to JP2025130622A priority patent/JP2025168357A/ja
Application granted granted Critical
Publication of JP7724693B2 publication Critical patent/JP7724693B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/617—Noise processing, e.g. detecting, correcting, reducing or removing noise for reducing electromagnetic interference, e.g. clocking noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/779—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/7795—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Electromagnetism (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Manipulation Of Pulses (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
JP2021189281A 2021-11-22 2021-11-22 クロック伝達回路、撮像素子、及びクロック伝達回路の製造方法 Active JP7724693B2 (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP2021189281A JP7724693B2 (ja) 2021-11-22 2021-11-22 クロック伝達回路、撮像素子、及びクロック伝達回路の製造方法
KR1020247019902A KR20240108480A (ko) 2021-11-22 2022-09-29 클록 전달 회로, 촬상 소자, 및 클록 전달 회로의 제조 방법
DE112022005614.2T DE112022005614T5 (de) 2021-11-22 2022-09-29 Taktübertragungsschaltung, bildgebendes Element und Verfahren zur Herstellung einer Taktübertragungsschaltung
US18/711,253 US12604116B2 (en) 2021-11-22 2022-09-29 Clock transmission circuit, imaging element, and method for manufacturing clock transmission circuit
GB2408578.9A GB2628256A (en) 2021-11-22 2022-09-29 Clock transmission circuit, imaging element, and method for manufacturing clock transmission circuit
CN202280076757.1A CN118266171A (zh) 2021-11-22 2022-09-29 时钟传递电路、摄像元件及时钟传递电路的制造方法
PCT/JP2022/036575 WO2023089964A1 (ja) 2021-11-22 2022-09-29 クロック伝達回路、撮像素子、及びクロック伝達回路の製造方法
TW111141076A TW202331808A (zh) 2021-11-22 2022-10-28 時脈傳達電路、攝像元件及時脈傳達電路之製造方法
JP2025130622A JP2025168357A (ja) 2021-11-22 2025-08-05 信号伝達回路及び信号伝達回路の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2021189281A JP7724693B2 (ja) 2021-11-22 2021-11-22 クロック伝達回路、撮像素子、及びクロック伝達回路の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2025130622A Division JP2025168357A (ja) 2021-11-22 2025-08-05 信号伝達回路及び信号伝達回路の製造方法

Publications (3)

Publication Number Publication Date
JP2023076093A JP2023076093A (ja) 2023-06-01
JP2023076093A5 JP2023076093A5 (https=) 2024-05-22
JP7724693B2 true JP7724693B2 (ja) 2025-08-18

Family

ID=86396770

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2021189281A Active JP7724693B2 (ja) 2021-11-22 2021-11-22 クロック伝達回路、撮像素子、及びクロック伝達回路の製造方法
JP2025130622A Pending JP2025168357A (ja) 2021-11-22 2025-08-05 信号伝達回路及び信号伝達回路の製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2025130622A Pending JP2025168357A (ja) 2021-11-22 2025-08-05 信号伝達回路及び信号伝達回路の製造方法

Country Status (8)

Country Link
US (1) US12604116B2 (https=)
JP (2) JP7724693B2 (https=)
KR (1) KR20240108480A (https=)
CN (1) CN118266171A (https=)
DE (1) DE112022005614T5 (https=)
GB (1) GB2628256A (https=)
TW (1) TW202331808A (https=)
WO (1) WO2023089964A1 (https=)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243939A (ja) 1999-02-17 2000-09-08 Nec Corp 半導体集積回路装置およびその設計方法
JP2001154371A (ja) 1999-11-30 2001-06-08 Nikon Corp 回路デバイスや表示デバイスの製造方法、及び大型ディスプレー装置
US20030218480A1 (en) 2002-04-05 2003-11-27 Indian St (Stmicroelectronics Pvt. Ltd.) Low power clock distribution scheme
JP2007060036A (ja) 2005-08-22 2007-03-08 Micron Technology Inc 構造化遅延スキューを用いたバッファリング技術
JP2007288788A (ja) 2006-04-18 2007-11-01 Agere Systems Inc 減少された挿入遅延を持つプログラマブル遅延回路
JP2016506106A (ja) 2012-11-15 2016-02-25 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 集積回路のための柔軟性がより高いクロックネットワークアーキテクチャ
US20160164508A1 (en) 2014-12-03 2016-06-09 Micron Technology, Inc. Apparatuses and methods for adjusting timing of signals
US20190081619A1 (en) 2017-09-12 2019-03-14 SK Hynix Inc. Duty cycle correction circuit and clock correction circuit including the same
WO2020241048A1 (ja) 2019-05-24 2020-12-03 ソニーセミコンダクタソリューションズ株式会社 回路システム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110708A (ja) 1999-10-08 2001-04-20 Nikon Corp 露光装置
US6255884B1 (en) * 2000-02-16 2001-07-03 Pairgain Technologies, Inc. Uniform clock timing circuit
JP5619434B2 (ja) * 2010-02-26 2014-11-05 パナソニック株式会社 固体撮像装置および撮像装置
KR102827206B1 (ko) * 2019-09-02 2025-07-01 삼성전자주식회사 클럭 트리를 포함하는 이미지 센서 및 어드레스 디코더, 이미지 센서를 포함하는 이미지 처리 시스템

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243939A (ja) 1999-02-17 2000-09-08 Nec Corp 半導体集積回路装置およびその設計方法
JP2001154371A (ja) 1999-11-30 2001-06-08 Nikon Corp 回路デバイスや表示デバイスの製造方法、及び大型ディスプレー装置
US20030218480A1 (en) 2002-04-05 2003-11-27 Indian St (Stmicroelectronics Pvt. Ltd.) Low power clock distribution scheme
JP2007060036A (ja) 2005-08-22 2007-03-08 Micron Technology Inc 構造化遅延スキューを用いたバッファリング技術
JP2007288788A (ja) 2006-04-18 2007-11-01 Agere Systems Inc 減少された挿入遅延を持つプログラマブル遅延回路
JP2016506106A (ja) 2012-11-15 2016-02-25 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 集積回路のための柔軟性がより高いクロックネットワークアーキテクチャ
US20160164508A1 (en) 2014-12-03 2016-06-09 Micron Technology, Inc. Apparatuses and methods for adjusting timing of signals
US20190081619A1 (en) 2017-09-12 2019-03-14 SK Hynix Inc. Duty cycle correction circuit and clock correction circuit including the same
WO2020241048A1 (ja) 2019-05-24 2020-12-03 ソニーセミコンダクタソリューションズ株式会社 回路システム

Also Published As

Publication number Publication date
US20250008241A1 (en) 2025-01-02
DE112022005614T5 (de) 2024-09-19
WO2023089964A1 (ja) 2023-05-25
US12604116B2 (en) 2026-04-14
CN118266171A (zh) 2024-06-28
TW202331808A (zh) 2023-08-01
KR20240108480A (ko) 2024-07-09
GB202408578D0 (en) 2024-07-31
JP2023076093A (ja) 2023-06-01
GB2628256A (en) 2024-09-18
JP2025168357A (ja) 2025-11-07

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