JP7618554B2 - オン抵抗が低減されたラテラルパワーデバイス - Google Patents
オン抵抗が低減されたラテラルパワーデバイス Download PDFInfo
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- JP7618554B2 JP7618554B2 JP2021535495A JP2021535495A JP7618554B2 JP 7618554 B2 JP7618554 B2 JP 7618554B2 JP 2021535495 A JP2021535495 A JP 2021535495A JP 2021535495 A JP2021535495 A JP 2021535495A JP 7618554 B2 JP7618554 B2 JP 7618554B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/343—Gate regions of field-effect devices having PN junction gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
- H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/652—Cross-sectional shapes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/654—Top-view layouts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/231—Shapes
- H10W72/232—Plan-view shape, i.e. in top view
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/247—Dispositions of multiple bumps
- H10W72/248—Top-view layouts, e.g. mirror arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/922—Bond pads being integral with underlying chip-level interconnections
- H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/944—Dispositions of multiple bond pads
- H10W72/9445—Top-view layouts, e.g. mirror arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
Landscapes
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862724106P | 2018-08-29 | 2018-08-29 | |
| US62/724,106 | 2018-08-29 | ||
| PCT/US2019/048834 WO2020047270A1 (en) | 2018-08-29 | 2019-08-29 | Lateral power device with reduced on-resistance |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| JP2021535625A JP2021535625A (ja) | 2021-12-16 |
| JP2021535625A5 JP2021535625A5 (https=) | 2022-09-02 |
| JPWO2020047270A5 JPWO2020047270A5 (https=) | 2022-09-02 |
| JP7618554B2 true JP7618554B2 (ja) | 2025-01-21 |
Family
ID=69639463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021535495A Active JP7618554B2 (ja) | 2018-08-29 | 2019-08-29 | オン抵抗が低減されたラテラルパワーデバイス |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US11101349B2 (https=) |
| EP (1) | EP3844820B1 (https=) |
| JP (1) | JP7618554B2 (https=) |
| KR (1) | KR102776818B1 (https=) |
| CN (1) | CN112913031A (https=) |
| TW (1) | TWI748233B (https=) |
| WO (1) | WO2020047270A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11749670B2 (en) * | 2020-05-18 | 2023-09-05 | Taiwan Semiconductor Manufacturing Company Limited | Power switch for backside power distribution |
| CN114664725B (zh) * | 2020-12-23 | 2025-07-29 | 华润微电子(重庆)有限公司 | GaN器件互联结构及其制备方法 |
| WO2023272674A1 (en) | 2021-07-01 | 2023-01-05 | Innoscience (Suzhou) Technology Co., Ltd. | Nitride-based multi-channel switching semiconductor device and method for manufacturing the same |
| CN115223965A (zh) * | 2022-06-29 | 2022-10-21 | 乂馆信息科技(上海)有限公司 | 一种大功率hemt器件和hemt器件拓扑连接结构 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012256885A (ja) | 2011-06-08 | 2012-12-27 | Great Wall Semiconductor Corp | 相互接続構造の珪化物層およびロープロファイルバンプを有するパワーmosfetを形成する半導体デバイスおよび方法 |
| WO2014188651A1 (ja) | 2013-05-20 | 2014-11-27 | パナソニックIpマネジメント株式会社 | 半導体装置 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6683380B2 (en) * | 2000-07-07 | 2004-01-27 | Texas Instruments Incorporated | Integrated circuit with bonding layer over active circuitry |
| JP2002164437A (ja) * | 2000-07-27 | 2002-06-07 | Texas Instruments Inc | ボンディングおよび電流配分を分散したパワー集積回路および方法 |
| US20030011045A1 (en) * | 2001-07-10 | 2003-01-16 | Tavanza, Inc. | Compact layout for a semiconductor device |
| US6972464B2 (en) * | 2002-10-08 | 2005-12-06 | Great Wall Semiconductor Corporation | Power MOSFET |
| KR100772920B1 (ko) * | 2006-02-20 | 2007-11-02 | 주식회사 네패스 | 솔더 범프가 형성된 반도체 칩 및 제조 방법 |
| KR101888369B1 (ko) * | 2010-10-12 | 2018-08-14 | 퀄컴 인코포레이티드 | 박형 기판을 갖는 수직 반도체 디바이스 |
| JP5580230B2 (ja) * | 2011-02-28 | 2014-08-27 | パナソニック株式会社 | 半導体装置 |
| US20140159130A1 (en) * | 2012-11-30 | 2014-06-12 | Enpirion, Inc. | Apparatus including a semiconductor device coupled to a decoupling device |
| EP2741324B1 (en) * | 2012-12-10 | 2018-10-31 | IMEC vzw | III nitride transistor with source connected heat-spreading plate and method of making the same |
| US8928037B2 (en) * | 2013-02-28 | 2015-01-06 | Power Integrations, Inc. | Heterostructure power transistor with AlSiN passivation layer |
| TWI515902B (zh) | 2013-09-10 | 2016-01-01 | 台達電子工業股份有限公司 | 半導體裝置 |
| TWI577022B (zh) * | 2014-02-27 | 2017-04-01 | 台達電子工業股份有限公司 | 半導體裝置與應用其之半導體裝置封裝體 |
| US10236236B2 (en) * | 2013-09-10 | 2019-03-19 | Delta Electronics, Inc. | Heterojunction semiconductor device for reducing parasitic capacitance |
| JP5669119B1 (ja) * | 2014-04-18 | 2015-02-12 | 株式会社パウデック | 半導体素子、電気機器、双方向電界効果トランジスタおよび実装構造体 |
| KR102272382B1 (ko) * | 2014-11-21 | 2021-07-05 | 삼성전자주식회사 | 반도체 소자 |
| US9324819B1 (en) | 2014-11-26 | 2016-04-26 | Delta Electronics, Inc. | Semiconductor device |
| DE112016007299T5 (de) * | 2016-09-30 | 2019-06-19 | Intel Corporation | Rückseiten-source/drain-austausch für halbleiterbauelemente mit metallisierung auf beiden seiten |
| US9972571B1 (en) * | 2016-12-15 | 2018-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Logic cell structure and method |
-
2019
- 2019-08-27 TW TW108130666A patent/TWI748233B/zh active
- 2019-08-29 KR KR1020217009126A patent/KR102776818B1/ko active Active
- 2019-08-29 EP EP19855368.7A patent/EP3844820B1/en active Active
- 2019-08-29 US US16/555,564 patent/US11101349B2/en active Active
- 2019-08-29 CN CN201980068467.0A patent/CN112913031A/zh active Pending
- 2019-08-29 JP JP2021535495A patent/JP7618554B2/ja active Active
- 2019-08-29 WO PCT/US2019/048834 patent/WO2020047270A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012256885A (ja) | 2011-06-08 | 2012-12-27 | Great Wall Semiconductor Corp | 相互接続構造の珪化物層およびロープロファイルバンプを有するパワーmosfetを形成する半導体デバイスおよび方法 |
| WO2014188651A1 (ja) | 2013-05-20 | 2014-11-27 | パナソニックIpマネジメント株式会社 | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3844820B1 (en) | 2025-09-17 |
| TWI748233B (zh) | 2021-12-01 |
| JP2021535625A (ja) | 2021-12-16 |
| US20200075726A1 (en) | 2020-03-05 |
| US11101349B2 (en) | 2021-08-24 |
| EP3844820A1 (en) | 2021-07-07 |
| EP3844820A4 (en) | 2022-06-01 |
| KR20210049891A (ko) | 2021-05-06 |
| KR102776818B1 (ko) | 2025-03-10 |
| TW202025482A (zh) | 2020-07-01 |
| WO2020047270A1 (en) | 2020-03-05 |
| CN112913031A (zh) | 2021-06-04 |
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