JP7478512B2 - 垂直型メモリ装置及びその製造方法 - Google Patents
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- 238000000034 method Methods 0.000 title description 66
- 238000004519 manufacturing process Methods 0.000 title description 41
- 239000011229 interlayer Substances 0.000 claims description 114
- 239000000758 substrate Substances 0.000 claims description 83
- 239000010410 layer Substances 0.000 claims description 65
- 230000000149 penetrating effect Effects 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 230000007423 decrease Effects 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 description 20
- 239000004065 semiconductor Substances 0.000 description 18
- 230000000903 blocking effect Effects 0.000 description 15
- 238000003860 storage Methods 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 235000010957 calcium stearoyl-2-lactylate Nutrition 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- -1 GaP Chemical class 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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Description
230、330 層間絶縁膜
240 ベースパターン
315 絶縁パターン
325 犠牲パターン
350 チャンネルホール
410 チャンネル
452、454、456 開口
462、464、466 ギャップ
485、700、710、720 ゲート電極
485a 導電パターン
485b パッド
510、515 コンタクトプラグ
510a コンタクトプラグ510の第1延在部
510b コンタクトプラグ510の第2延在部
520 共通ソースライン(CSL)
I セルアレイ領域
II パッド領域
III 周辺領域
Claims (17)
- 基板の上面に垂直な第1方向に沿って前記基板上に積層されて上層に行くほど前記基板の上面に平行な第2方向への延在長さが徐々に減る階段形状に配置され、各々の前記第2方向の端部に形成されたパッドが他の部分に比べて大きい厚さを有する複数のゲート電極であり、各ゲート電極の前記パッドの底面全体が前記他の部分の底面と実質的に同一面内にある、複数のゲート電極と、
前記複数のゲート電極を貫通して前記第1方向に延在されたチャンネルと、
前記複数のゲート電極を貫通して前記第1方向に延在され、かつ前記複数のゲート電極のうち、最上層に形成された第1ゲート電極の前記パッドと前記大きい厚さ全体で接触して、前記第1ゲート電極に電気的に連結され、前記複数のゲート電極のうち、前記第1ゲート電極以外の他のゲート電極とは電気的に絶縁されたコンタクトプラグと、
を含む垂直型メモリ装置。 - 前記コンタクトプラグは前記他のゲート電極の各々の前記パッドでない部分を貫通する、請求項1に記載の垂直型メモリ装置。
- 前記コンタクトプラグと前記他のゲート電極の各々との間に形成されて前記コンタクトプラグの側壁を囲む第1絶縁パターンをさらに含む、請求項1に記載の垂直型メモリ装置。
- 前記基板上に形成されて前記複数のゲート電極を貫通し、前記第2方向に延在される共通ソースライン(CSL)をさらに含む、請求項1に記載の垂直型メモリ装置。
- 前記コンタクトプラグ及び前記CSLは実質的に互いに同一な物質を含む、請求項4に記載の垂直型メモリ装置。
- 前記ゲート電極は前記コンタクトプラグ及び前記CSLと実質的に互いに同一な物質を含む、請求項5に記載の垂直型メモリ装置。
- 前記CSLと前記複数のゲート電極の各々との間に形成されて前記CSLの側壁を囲む第2絶縁パターンをさらに含む、請求項4に記載の垂直型メモリ装置。
- 前記基板上に形成された回路パターンと、
前記基板上に形成されて前記回路パターンをカバーする層間絶縁膜と、
前記層間絶縁膜上に形成されたベースパターンをさらに含み、
前記ゲート電極及び前記チャンネルは前記ベースパターン上に形成され、前記コンタクトプラグは前記層間絶縁膜を少なくとも部分的に貫通して前記回路パターンに電気的に連結される、請求項4に記載の垂直型メモリ装置。 - 前記ベースパターンはシリコンを含む、請求項8に記載の垂直型メモリ装置。
- 前記基板は、
前記第2方向への中央に形成されたセルアレイ領域と、
前記第2方向に両端に形成されたパッド領域を含み、
前記チャンネル及び前記CSLは前記基板のセルアレイ領域上に形成され、前記ゲート電極の前記パッド及び前記コンタクトプラグは前記基板のパッド領域上に形成される、請求項8に記載の垂直型メモリ装置。 - 前記ベースパターンは、前記基板のセルアレイ領域上のみに形成される、請求項10に記載の垂直型メモリ装置。
- セルアレイ領域及びパッド領域を含む基板上に形成された回路パターンと、
前記回路パターンをカバーする層間絶縁膜と、
前記基板のセルアレイ領域上で前記層間絶縁膜上に形成されたベースパターンと、
前記ベースパターン及び前記層間絶縁膜上に前記基板の上面に垂直な第1方向に互いに離隔するように複数の層に各々配置された複数のゲート電極であり、当該複数のゲート電極は、前記パッド領域において、上層に行くほど前記基板の上面に平行な第2方向への延在長さが徐々に減る階段形状に配置され、各ゲート電極の前記第2方向の端部に形成されたパッドが他の部分に比べて大きい厚さを有し、各ゲート電極の前記パッドの底面全体が前記他の部分の底面と実質的に同一面内にある、複数のゲート電極と、
前記基板のセルアレイ領域上で前記複数のゲート電極を貫通するチャンネルと、
前記基板のパッド領域上で前記複数のゲート電極のうちの複数個の一部及び前記層間絶縁膜を貫通して前記回路パターンに電気的に連結されたコンタクトプラグと、
を含み、
前記コンタクトプラグは、前記貫通するゲート電極のうちの最上層に形成された1つのゲート電極のみの前記パッドに、前記大きい厚さ全体で接触して電気的に連結される、
垂直型メモリ装置。 - 前記複数のゲート電極の各々の前記パッドは、他の部分より上面の高さが高い、請求項12に記載の垂直型メモリ装置。
- 前記コンタクトプラグは、前記パッドを通じて前記複数のゲート電極のうちの1つに電気的に連結される、請求項12に記載の垂直型メモリ装置。
- 前記コンタクトプラグは、
前記第1方向に延在される第1延在部と、
前記第1延在部に連結されて、前記第1延在部の一部の側壁を囲み、前記基板の上面に平行な第2方向に延在される第2延在部を含む、請求項12に記載の垂直型メモリ装置。 - 前記コンタクトプラグは、電気的に連結されたゲート電極より下層に配置されたゲート電極とは、これらの間に形成された絶縁パターンにより電気的に絶縁される、請求項12に記載の垂直型メモリ装置。
- 基板の上面に垂直な第1方向に沿って前記基板上に積層され、各々の第1部分が残りの部分に比べて大きい厚さを有する複数のゲート電極であり、各ゲート電極の前記第1部分の底面全体が前記残りの部分の底面と実質的に同一面内にある、複数のゲート電極と、
前記複数のゲート電極を貫通して前記第1方向に各々延在された複数のチャンネルと、
各々が前記複数のゲート電極のうちの複数個の一部を貫通して前記第1方向に延在され、かつ各々が前記貫通するゲート電極のうちの最上層に形成された1つの前記第1部分を貫通してこれに前記大きい厚さ全体で接触して電気的に連結され、前記貫通するゲート電極のうちの残りのものとは電気的に絶縁された、複数のコンタクトプラグと、
を含み、
前記複数のゲート電極の各々の前記第1部分は該ゲート電極の端部に形成され、前記第1部分の上面は残り部分の上面より高い、
垂直型メモリ装置。
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KR102649568B1 (ko) * | 2019-05-03 | 2024-03-21 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법과, 상기 반도체 장치를 포함하는 메모리 장치 및 시스템 |
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JP2021150463A (ja) | 2020-03-18 | 2021-09-27 | キオクシア株式会社 | 半導体装置 |
CN111370416B (zh) * | 2020-03-23 | 2022-09-23 | 长江存储科技有限责任公司 | 三维存储器及三维存储器制作方法 |
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CN111819690B (zh) | 2020-06-05 | 2021-05-14 | 长江存储科技有限责任公司 | 三维存储器件中的阶梯结构及用于形成其的方法 |
CN111919299B (zh) | 2020-06-05 | 2021-08-17 | 长江存储科技有限责任公司 | 三维存储器件中的阶梯结构及其形成方法 |
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Publication number | Publication date |
---|---|
US20200411546A1 (en) | 2020-12-31 |
SG10201900586VA (en) | 2019-11-28 |
US20230292515A1 (en) | 2023-09-14 |
KR102624625B1 (ko) | 2024-01-12 |
JP2019192905A (ja) | 2019-10-31 |
US20190326316A1 (en) | 2019-10-24 |
EP3557622A3 (en) | 2019-11-20 |
EP3557622A2 (en) | 2019-10-23 |
KR20190122372A (ko) | 2019-10-30 |
CN110391248A (zh) | 2019-10-29 |
EP3557622B1 (en) | 2020-05-13 |
US11696442B2 (en) | 2023-07-04 |
US10748923B2 (en) | 2020-08-18 |
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