JP7450006B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7450006B2 JP7450006B2 JP2022181139A JP2022181139A JP7450006B2 JP 7450006 B2 JP7450006 B2 JP 7450006B2 JP 2022181139 A JP2022181139 A JP 2022181139A JP 2022181139 A JP2022181139 A JP 2022181139A JP 7450006 B2 JP7450006 B2 JP 7450006B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- terminal
- semiconductor device
- back surface
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 229
- 229920005989 resin Polymers 0.000 claims description 263
- 239000011347 resin Substances 0.000 claims description 263
- 238000007789 sealing Methods 0.000 claims description 96
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 2
- 238000006073 displacement reaction Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/29166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
厚さ方向において互いに反対側を向く素子主面および素子裏面と、前記素子裏面に配置された第1電極と、前記素子主面に配置された第2電極とを有する半導体素子と、
前記半導体素子の前記第1電極が接合される搭載部主面、および、前記厚さ方向において前記搭載部主面とは反対側を向く搭載部裏面を有する搭載部と、前記搭載部を介して前記第1電極と導通する第1端子とを有する第1リードと、
前記第2電極と導通する第2端子を有する第2リードと、
前記第1リードおよび前記第2リードの一部ずつと、前記半導体素子とを覆う封止樹脂と、を備え、
前記第1端子および前記第2端子は、前記封止樹脂から突出し、
前記封止樹脂は、厚さ方向において互いに反対側を向く樹脂主面および樹脂裏面と、前記樹脂主面および前記樹脂裏面を繋ぎ、かつ、前記第1端子および前記第2端子が突出する方向を向く樹脂端面と、前記樹脂主面および前記樹脂裏面を繋ぎ、かつ、前記樹脂端面に繋がる1対の樹脂側面とを備え、
前記搭載部裏面は前記樹脂裏面から露出し、
前記封止樹脂は、前記樹脂裏面側において、前記第2端子と前記樹脂端面との境界と、前記搭載部裏面との間に、前記樹脂裏面から前記厚さ方向に離れた部分を有する裏面変位部を備える、半導体装置。
付記2.
前記裏面変位部は、前記厚さ方向視において、前記第1リードに重ならない、付記1に記載の半導体装置。
付記3.
前記裏面変位部は、前記第2端子側の前記樹脂側面まで延びている、付記1または2に記載の半導体装置。
付記4.
前記裏面変位部は、前記樹脂側面に平行な断面が四角形状の溝である、付記1ないし3のいずれか1つに記載の半導体装置。
付記5.
前記裏面変位部は、前記樹脂裏面から突出しており、前記樹脂側面に平行な断面が四角形状である、付記1ないし3のいずれか1つに記載の半導体装置。
付記6.
前記裏面変位部は複数の裏面変位部を含む、付記1ないし5のいずれか1つに記載の半導体装置。
付記7.
前記第1リードは、前記搭載部と前記第1端子とに繋がる連結部をさらに備え、前記連結部は、前記搭載部および前記第1端子に対して傾斜している、付記1ないし6のいずれか1つに記載の半導体装置。
付記8.
前記封止樹脂は、前記樹脂主面から前記樹脂裏面まで貫通する樹脂貫通孔を備え、前記搭載部は、前記搭載部主面から前記搭載部裏面まで貫通する搭載部貫通孔を備え、前記樹脂貫通孔は前記搭載部貫通孔の内側に位置する、付記1ないし7のいずれか1つに記載の半導体装置。
付記9.
前記封止樹脂は、前記樹脂端面から突出する端面凸部を備え、前記第2端子は、前記端面凸部から突出する、付記1ないし8のいずれか1つに記載の半導体装置。
付記10.
前記封止樹脂は、前記端面凸部から離間し、かつ、前記樹脂端面から突出する第2の端面凸部を備え、前記第1端子は、前記第2の端面凸部から突出する、付記9に記載の半導体装置。
付記11.
前記半導体素子は、ダイオードである、付記1ないし10のいずれか1つに記載の半導体装置。
付記12.
第3リードをさらに備える構成において、
前記半導体素子は、前記素子主面に配置された第3電極を備えており、前記第3リードは、前記第3電極と導通する第3端子を備えている、付記1ないし10のいずれか1つに記載の半導体装置。
付記13.
前記封止樹脂は、前記樹脂裏面側において、前記第3端子と前記樹脂端面との境界と、前記搭載部裏面との間に、前記樹脂裏面から前記厚さ方向に離れた部分を有する第2の裏面変位部を備える、付記12に記載の半導体装置。
付記14.
前記裏面変位部は、前記第3端子と前記樹脂端面との境界と、前記搭載部裏面との間まで延びる、付記12に記載の半導体装置。
付記15.
前記半導体素子は、トランジスタである、付記11ないし14のいずれか1つに記載の半導体装置。
付記16.
第4リードをさらに備える構成において、
前記半導体素子は、第4電極を備え、前記第4リードは、前記第4電極と導通する第4端子を備える、付記12に記載の半導体装置。
Claims (15)
- 厚さ方向において互いに反対側を向く素子主面および素子裏面と、前記素子裏面に配置された第1電極と、前記素子主面に配置された第2電極とを有する半導体素子と、
前記半導体素子の前記第1電極が接合される搭載部主面、および、前記厚さ方向において前記搭載部主面とは反対側を向く搭載部裏面を有する搭載部と、前記搭載部を介して前記第1電極に電流を流す第1端子とを有する第1リードと、
前記第2電極と導通する第2端子を有する第2リードと、
前記第1リードおよび前記第2リードの各々の一部と、前記半導体素子とを覆う封止樹脂と、
を備え、
前記第1端子および前記第2端子は、前記封止樹脂から突出し、
前記封止樹脂は、前記厚さ方向において互いに反対側を向く樹脂主面および樹脂裏面と、前記樹脂主面および前記樹脂裏面を繋ぎ、かつ、前記第1端子および前記第2端子が突出する方向を向く樹脂端面と、前記樹脂主面および前記樹脂裏面を繋ぎ、かつ、前記樹脂端面に繋がる1対の樹脂側面とを備え、
前記搭載部裏面は前記樹脂裏面から露出し、
前記封止樹脂は、前記樹脂裏面側において、前記第2端子の前記封止樹脂から露出した部分と前記封止樹脂との境界と、前記搭載部裏面との間に、凹部を備え、
前記凹部は、前記1対の樹脂側面の一方にのみ達している、
る、半導体装置。 - 前記封止樹脂は、前記樹脂端面とは反対側を向く樹脂第2端面をさらに備え、
前記第1リードは、前記樹脂第2端面から露出しない、請求項1に記載の半導体装置。 - 前記凹部は、前記厚さ方向視において、前記第1リードに重ならない、請求項1または2に記載の半導体装置。
- 前記凹部は、前記樹脂側面に平行な断面が四角形状である、請求項1ないし3のいずれか1つに記載の半導体装置。
- 前記凹部は、平坦な単一の底面を含む、請求項1ないし4のいずれか1つに記載の半導体装置。
- 前記第1リードは、前記搭載部と前記第1端子とに繋がる連結部を備え、前記連結部は、前記搭載部および前記第1端子に対して傾斜している、請求項1ないし5のいずれか1つに記載の半導体装置。
- 前記封止樹脂は、前記樹脂主面から前記樹脂裏面まで貫通する樹脂貫通孔を備え、前記搭載部は、前記搭載部主面から前記搭載部裏面まで貫通する搭載部貫通孔を備え、前記樹脂貫通孔は前記搭載部貫通孔の内側に位置する、請求項1ないし6のいずれか1つに記載の半導体装置。
- 前記封止樹脂は、前記樹脂端面から突出する端面凸部を備え、前記第2端子は、前記端面凸部から突出する、請求項1ないし7のいずれか1つに記載の半導体装置。
- 前記封止樹脂は、前記端面凸部から離間し、かつ、前記樹脂端面から突出する第2の端面凸部を備え、前記第1端子は、前記第2の端面凸部から突出する、請求項8に記載の半導体装置。
- 前記半導体素子は、ダイオードである、請求項1ないし9のいずれか1つに記載の半導体装置。
- 第3リードをさらに備える構成において、
前記半導体素子は、前記素子主面に配置された第3電極を備え、前記第3リードは、前記第3電極と導通する第3端子を備える、請求項1ないし9のいずれか1つに記載の半導体装置。 - 前記封止樹脂は、前記樹脂裏面側において、前記第3端子と前記樹脂端面との境界と、前記搭載部裏面との間に、第2の凹部を備え、
前記凹部と前記第2の凹部とは、前記1対の樹脂側面が並ぶ方向において離間している、請求項11に記載の半導体装置。 - 前記凹部は、前記第3端子と前記樹脂端面との境界と、前記搭載部裏面との間まで延びる、請求項11に記載の半導体装置。
- 前記半導体素子は、トランジスタである、請求項11ないし13のいずれか1つに記載の半導体装置。
- 第4リードをさらに備える構成において、
前記半導体素子は、第4電極を備え、前記第4リードは、前記第4電極と導通する第4端子を備える、請求項11に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2024032255A JP2024059956A (ja) | 2018-09-19 | 2024-03-04 | 半導体装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018174815 | 2018-09-19 | ||
JP2018174815 | 2018-09-19 | ||
JP2020548551A JPWO2020059751A1 (ja) | 2018-09-19 | 2019-09-18 | 半導体装置 |
PCT/JP2019/036556 WO2020059751A1 (ja) | 2018-09-19 | 2019-09-18 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020548551A Division JPWO2020059751A1 (ja) | 2018-09-19 | 2019-09-18 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2024032255A Division JP2024059956A (ja) | 2018-09-19 | 2024-03-04 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2023015278A JP2023015278A (ja) | 2023-01-31 |
JP7450006B2 true JP7450006B2 (ja) | 2024-03-14 |
Family
ID=69887237
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020548551A Pending JPWO2020059751A1 (ja) | 2018-09-19 | 2019-09-18 | 半導体装置 |
JP2022181139A Active JP7450006B2 (ja) | 2018-09-19 | 2022-11-11 | 半導体装置 |
JP2024032255A Pending JP2024059956A (ja) | 2018-09-19 | 2024-03-04 | 半導体装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020548551A Pending JPWO2020059751A1 (ja) | 2018-09-19 | 2019-09-18 | 半導体装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2024032255A Pending JP2024059956A (ja) | 2018-09-19 | 2024-03-04 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (4) | US11502014B2 (ja) |
JP (3) | JPWO2020059751A1 (ja) |
CN (1) | CN112703594A (ja) |
DE (2) | DE112019005278T5 (ja) |
WO (1) | WO2020059751A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112022004054T5 (de) * | 2021-12-01 | 2024-08-01 | Rohm Co., Ltd. | Halbleiterbauteil |
WO2023100659A1 (ja) * | 2021-12-01 | 2023-06-08 | ローム株式会社 | 半導体装置 |
WO2024029235A1 (ja) * | 2022-08-01 | 2024-02-08 | ローム株式会社 | 半導体装置 |
WO2024154566A1 (ja) * | 2023-01-16 | 2024-07-25 | ローム株式会社 | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073743A (ja) | 2005-09-07 | 2007-03-22 | Denso Corp | 半導体装置 |
JP2017147433A (ja) | 2015-12-16 | 2017-08-24 | ローム株式会社 | 半導体装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2708191B2 (ja) * | 1988-09-20 | 1998-02-04 | 株式会社日立製作所 | 半導体装置 |
JP2567961B2 (ja) * | 1989-12-01 | 1996-12-25 | 株式会社日立製作所 | 半導体装置及びリ−ドフレ−ム |
US5200364A (en) * | 1990-01-26 | 1993-04-06 | Texas Instruments Incorporated | Packaged integrated circuit with encapsulated electronic devices |
JP2932785B2 (ja) * | 1991-09-20 | 1999-08-09 | 富士通株式会社 | 半導体装置 |
JPH0897333A (ja) * | 1994-09-29 | 1996-04-12 | Tokin Corp | 半導体モールドパッケージ |
US6277225B1 (en) * | 1996-03-13 | 2001-08-21 | Micron Technology, Inc. | Stress reduction feature for LOC lead frame |
EP0817261B1 (en) * | 1996-06-28 | 2003-04-23 | STMicroelectronics S.r.l. | Method for manufacturing plastic package for electronic device having a fully insulated dissipator |
TW428295B (en) * | 1999-02-24 | 2001-04-01 | Matsushita Electronics Corp | Resin-sealing semiconductor device, the manufacturing method and the lead frame thereof |
KR101867106B1 (ko) * | 2010-03-30 | 2018-06-12 | 다이니폰 인사츠 가부시키가이샤 | Led용 수지 부착 리드 프레임, 반도체 장치, 반도체 장치의 제조 방법 및 led용 수지 부착 리드 프레임의 제조 방법 |
KR101778832B1 (ko) * | 2010-11-02 | 2017-09-14 | 다이니폰 인사츠 가부시키가이샤 | Led 소자 탑재용 리드 프레임, 수지 부착 리드 프레임, 반도체 장치의 제조 방법 및 반도체 소자 탑재용 리드 프레임 |
JP5975911B2 (ja) | 2013-03-15 | 2016-08-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6154342B2 (ja) * | 2013-12-06 | 2017-06-28 | トヨタ自動車株式会社 | 半導体装置 |
EP3128539B1 (en) * | 2014-03-27 | 2020-01-08 | Renesas Electronics Corporation | Semiconductor device manufacturing method and semiconductor device |
JP6483498B2 (ja) * | 2014-07-07 | 2019-03-13 | ローム株式会社 | 電子装置およびその実装構造 |
US9711700B2 (en) * | 2014-12-26 | 2017-07-18 | Nichia Corporation | Light emitting device and method for producing the same |
JP6595325B2 (ja) * | 2015-12-04 | 2019-10-23 | トヨタ自動車株式会社 | 半導体装置 |
JP6517682B2 (ja) * | 2015-12-17 | 2019-05-22 | トヨタ自動車株式会社 | 半導体装置 |
JP6973730B2 (ja) * | 2016-07-08 | 2021-12-01 | ローム株式会社 | 半導体装置の製造方法および半導体装置 |
US10535812B2 (en) * | 2017-09-04 | 2020-01-14 | Rohm Co., Ltd. | Semiconductor device |
-
2019
- 2019-09-18 JP JP2020548551A patent/JPWO2020059751A1/ja active Pending
- 2019-09-18 US US17/268,277 patent/US11502014B2/en active Active
- 2019-09-18 DE DE112019005278.0T patent/DE112019005278T5/de active Pending
- 2019-09-18 CN CN201980059614.8A patent/CN112703594A/zh active Pending
- 2019-09-18 DE DE212019000110.6U patent/DE212019000110U1/de active Active
- 2019-09-18 WO PCT/JP2019/036556 patent/WO2020059751A1/ja active Application Filing
-
2022
- 2022-10-05 US US17/960,632 patent/US11854923B2/en active Active
- 2022-11-11 JP JP2022181139A patent/JP7450006B2/ja active Active
-
2023
- 2023-05-15 US US18/317,699 patent/US12051633B2/en active Active
-
2024
- 2024-03-04 JP JP2024032255A patent/JP2024059956A/ja active Pending
- 2024-06-24 US US18/752,182 patent/US20240347405A1/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073743A (ja) | 2005-09-07 | 2007-03-22 | Denso Corp | 半導体装置 |
JP2017147433A (ja) | 2015-12-16 | 2017-08-24 | ローム株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
DE212019000110U1 (de) | 2020-03-05 |
US20230282535A1 (en) | 2023-09-07 |
WO2020059751A1 (ja) | 2020-03-26 |
CN112703594A (zh) | 2021-04-23 |
JP2023015278A (ja) | 2023-01-31 |
US20210320044A1 (en) | 2021-10-14 |
JP2024059956A (ja) | 2024-05-01 |
US11854923B2 (en) | 2023-12-26 |
DE112019005278T5 (de) | 2021-07-29 |
US20230030063A1 (en) | 2023-02-02 |
JPWO2020059751A1 (ja) | 2021-08-30 |
US20240347405A1 (en) | 2024-10-17 |
US11502014B2 (en) | 2022-11-15 |
US12051633B2 (en) | 2024-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7450006B2 (ja) | 半導体装置 | |
JP7441287B2 (ja) | 半導体装置 | |
JP7137558B2 (ja) | 半導体装置 | |
JP7546034B2 (ja) | 半導体装置 | |
JPH09260550A (ja) | 半導体装置 | |
US10229884B2 (en) | Semiconductor device | |
JP7367154B2 (ja) | 半導体装置 | |
JP7137955B2 (ja) | 半導体装置 | |
US20200091033A1 (en) | Electric device and heat radiator | |
EP3584829A1 (en) | Electronic device | |
US12009287B2 (en) | Semiconductor device with packaging material and metal member protruding from the packaging material | |
CN115668488A (zh) | 半导体模块的安装结构 | |
US7466016B2 (en) | Bent lead transistor | |
JP6292066B2 (ja) | 電力用半導体装置 | |
WO2024154566A1 (ja) | 半導体装置 | |
WO2023021938A1 (ja) | 半導体装置 | |
JP6732477B2 (ja) | Led発光装置 | |
CN218274579U (zh) | 一种GaN封装芯片结构与电子装置 | |
WO2023136074A1 (ja) | 半導体装置 | |
US12021323B2 (en) | Semiconductor module | |
US20230011627A1 (en) | Semiconductor device | |
WO2024128062A1 (ja) | 半導体装置 | |
JP2007027402A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20221111 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20230817 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20231003 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20231117 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20240206 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20240304 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7450006 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |