JP7438973B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP7438973B2
JP7438973B2 JP2020558235A JP2020558235A JP7438973B2 JP 7438973 B2 JP7438973 B2 JP 7438973B2 JP 2020558235 A JP2020558235 A JP 2020558235A JP 2020558235 A JP2020558235 A JP 2020558235A JP 7438973 B2 JP7438973 B2 JP 7438973B2
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JP
Japan
Prior art keywords
resin layer
bumps
bump
bumped
semiconductor device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020558235A
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English (en)
Japanese (ja)
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JPWO2020110620A1 (ja
Inventor
圭亮 四宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lintec Corp
Original Assignee
Lintec Corp
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Publication date
Application filed by Lintec Corp filed Critical Lintec Corp
Publication of JPWO2020110620A1 publication Critical patent/JPWO2020110620A1/ja
Application granted granted Critical
Publication of JP7438973B2 publication Critical patent/JP7438973B2/ja
Active legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Wire Bonding (AREA)
JP2020558235A 2018-11-27 2019-11-05 半導体装置の製造方法 Active JP7438973B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2018221213 2018-11-27
JP2018221213 2018-11-27
PCT/JP2019/043200 WO2020110620A1 (ja) 2018-11-27 2019-11-05 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPWO2020110620A1 JPWO2020110620A1 (ja) 2021-10-14
JP7438973B2 true JP7438973B2 (ja) 2024-02-27

Family

ID=70854304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020558235A Active JP7438973B2 (ja) 2018-11-27 2019-11-05 半導体装置の製造方法

Country Status (5)

Country Link
JP (1) JP7438973B2 (zh)
KR (1) KR20210095863A (zh)
CN (1) CN113169064A (zh)
TW (1) TW202030806A (zh)
WO (1) WO2020110620A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7422410B2 (ja) * 2021-07-29 2024-01-26 日化精工株式会社 ウェーハ上のデバイスの保護処理方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133669A (ja) 1998-10-26 2000-05-12 Sony Corp 半導体装置の製造方法
JP2001250902A (ja) 2000-03-08 2001-09-14 Toshiba Corp 半導体パッケージ及びその製造方法
JP2004319656A (ja) 2003-04-15 2004-11-11 Nec Toppan Circuit Solutions Inc ウエハーレベルｃｓｐの製造方法
JP2006261245A (ja) 2005-03-15 2006-09-28 Shinko Electric Ind Co Ltd 配線基板の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6139377B2 (ja) * 2013-10-28 2017-05-31 国立大学法人東北大学 センサ装置およびその製造方法
JP6698647B2 (ja) 2015-05-29 2020-05-27 リンテック株式会社 半導体装置の製造方法
JP2017084903A (ja) 2015-10-26 2017-05-18 リンテック株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133669A (ja) 1998-10-26 2000-05-12 Sony Corp 半導体装置の製造方法
JP2001250902A (ja) 2000-03-08 2001-09-14 Toshiba Corp 半導体パッケージ及びその製造方法
JP2004319656A (ja) 2003-04-15 2004-11-11 Nec Toppan Circuit Solutions Inc ウエハーレベルｃｓｐの製造方法
JP2006261245A (ja) 2005-03-15 2006-09-28 Shinko Electric Ind Co Ltd 配線基板の製造方法

Also Published As

Publication number Publication date
KR20210095863A (ko) 2021-08-03
TW202030806A (zh) 2020-08-16
CN113169064A (zh) 2021-07-23
JPWO2020110620A1 (ja) 2021-10-14
WO2020110620A1 (ja) 2020-06-04

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