JP7438664B2 - ウェハ合成物および半導体コンポーネントの製造方法 - Google Patents
ウェハ合成物および半導体コンポーネントの製造方法 Download PDFInfo
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Description
Claims (27)
- 半導体コンポーネントの製造方法であって、
前記方法は、ウェハ合成物(900)を提供するステップを含んでおり、
前記ウェハ合成物(900)は、ドナー基板(100)と、補助基板(300)と、前記補助基板(300)と前記ドナー基板(100)との間に配置されている分離層(250)と、を含んでおり、前記分離層(250)は、支持構造体(252)および犠牲材料(255)を有しており、前記犠牲材料(255)は、前記支持構造体(252)の要素間に横方向に形成されており、前記犠牲材料(255)は、前記支持構造体(252)における前記要素間の間隙を通じて相互に接合されており、
前記支持構造体(252)は、最大で、前記ドナー基板(100)の表面(101)または前記補助基板(300)の表面(301)の全体の50%を占領し、
前記方法は、前記支持構造体(252)に関する前記犠牲材料(255)の選択的な除去を含む、前記補助基板(300)を前記ドナー基板(100)から分離するステップを含んでおり、
前記ウェハ合成物(900)を提供するステップは、
前記分離層(250)を前記ドナー基板(100)または前記補助基板(300)上に形成するステップと、
前記分離層(250)が前記補助基板(300)と前記ドナー基板(100)との間に配置されるように、前記補助基板(300)を前記ドナー基板(100)に接合するステップと、
を含んでいる、
方法。 - 前記分離層(250)を形成するステップは、
前記支持構造体(252)の要素を形成するステップと、
前記支持構造体(252)の前記要素間に形成されたチャンバ(251)を前記犠牲材料(255)で充填するステップと、
を含んでいる、
請求項1記載の方法。 - 分離の前に、コンポーネント層(110)内に、前記半導体コンポーネントの機能的な要素(190)を形成し、前記コンポーネント層(110)は、前記ドナー基板(100)またはシード層(111)を含んでおり、前記シード層(111)は、前記ドナー基板(100)から分割され、エピタキシャル層(112)が前記シード層(111)上に成長する、
請求項1記載の方法。 - 前記支持構造体(252)は、窒化ケイ素、酸化ケイ素、酸化アルミニウムおよび/またはケイ素を含んでいる、
請求項1記載の方法。 - 前記方法は、さらに、前記ドナー基板(100)を前記分離層(250)に平行な分割面に沿って、シード層(111)と主要部分(180)とに分割するステップを含んでおり、分割の後に前記ドナー基板(100)の前記シード層(111)を前記補助基板(300)に接合し、前記ドナー基板(100)の前記主要部分(180)を前記シード層(111)から切り離す、
請求項1記載の方法。 - 軽イオンを注入することによって欠陥層(170)を前記ドナー基板(100)内に形成し、分割を前記欠陥層(170)に沿って実行する、
請求項5記載の方法。 - 前記分離層(250)の所まで達する鉛直方向の開口部(265)を前記シード層(111)内に形成する、
請求項5記載の方法。 - 前記方法は、さらに、エピタキシャル層(112)を前記シード層(111)上に成長させるステップを含んでいる、
請求項5記載の方法。 - 深い開口部(266)を形成し、前記深い開口部(266)は、前記エピタキシャル層(112)および前記シード層(111)を通って前記分離層(250)内に達し、
前記犠牲材料(255)および/または前記犠牲材料(255)の分解産物を、前記深い開口部(266)を通じて除去する、
請求項8記載の方法。 - 前記分離層(250)に達する鉛直方向の補助開口部(305)を前記補助基板(300)内に形成し、前記犠牲材料(255)および/または前記犠牲材料(255)の分解産物を、前記鉛直方向の補助開口部(305)を通じて除去する、
請求項1記載の方法。 - 前記犠牲材料(255)の除去は、前記犠牲材料(255)の熱分解を含んでいる、
請求項1記載の方法。 - 前記犠牲材料(255)の除去は、前記犠牲材料(255)の化学分解または化学溶解を含んでいる、
請求項1記載の方法。 - 前記支持構造体(252)は、前記分離層(250)の外縁に沿って支持リング(2521)を有しており、前記分離は、前記支持リング(2521)の開放を含んでいる、
請求項1記載の方法。 - 前記補助基板(300)を前記ドナー基板(100)から分離するステップは、
液体を前記支持構造体(252)の前記要素間に導入するステップと、
前記液体を導入するステップの後、前記液体を凍結させるステップと、
を含んでいる、
請求項1記載の方法。 - 前記補助基板(300)を前記ドナー基板(100)から分離するステップは、エッチング媒体を前記支持構造体(252)の前記要素間に導入するステップを含んでいる、
請求項1記載の方法。 - 前記エッチング媒体は、前記支持構造体(252)の材料を溶かす酸である、
請求項15記載の方法。 - 前記支持構造体(252)は、前記ドナー基板(100)に被着されている、
請求項1記載の方法。 - 前記支持構造体(252)は、前記補助基板(300)に被着されている、
請求項1記載の方法。 - 前記方法は、
前記分離層(250)上に補助層(260)を被着するステップと、
その後、前記補助基板(300)を前記ドナー基板(100)に接合するステップと、
をさらに含んでいる、
請求項1記載の方法。 - 前記方法は、
前記補助基板(300)上に形成されている前記分離層(250)の上にメタライゼーション層(270)を被着するステップと、
その後、前記補助基板(300)を前記ドナー基板(100)に接合するステップと、
をさらに含んでいる、
請求項1記載の方法。 - 前記ドナー基板(100)と前記補助基板(300)とは、同じ半導体材料を含んでいる、
請求項1記載の方法。 - 前記ドナー基板(100)は、第1の結晶性半導体材料を含んでおり、前記補助基板(300)は、第2の結晶性半導体材料を含んでおり、
前記第2の結晶性半導体材料は、前記第1の結晶性半導体材料と同じ要素を有しており、
前記第1の結晶性半導体材料と前記第2の結晶性半導体材料とは、ドーピング、結晶のタイプ、ポリタイプまたは結晶粒界の存在および/または欠如のうちの少なくとも1つによって相違している、
請求項1記載の方法。 - ウェハ合成物であって、前記ウェハ合成物は、
ドナー基板(100)と、
補助基板(300)と、
前記補助基板(300)を前記ドナー基板(100)に接合する分離層(250)と、
を含んでおり、
前記分離層(250)は、支持構造体(252)および犠牲材料(255)を有しており、前記犠牲材料(255)は、前記支持構造体(252)の要素間に横方向に形成されており、前記犠牲材料(255)は、前記支持構造体(252)における前記要素間の間隙を通じて相互に接合されており、
前記支持構造体(252)は、最大で、前記ドナー基板(100)の表面(101)または前記補助基板(300)の表面(301)の全体の50%を占領する、
ウェハ合成物。 - 前記ドナー基板(100)の第1の結晶性半導体材料と前記補助基板(300)の第2の結晶性半導体材料とは、ドーピング、結晶のタイプ、ポリタイプおよび/または結晶粒界の存在または欠如のうちの少なくとも1つによって相違している、
請求項23記載のウェハ合成物。 - 前記第1の結晶性半導体材料と前記第2の結晶性半導体材料とは、同じ要素から形成されている、
請求項24記載のウェハ合成物。 - 前記支持構造体(252)は、前記分離層(250)の外縁に沿って支持リング(2521)を有している、
請求項23記載のウェハ合成物。 - 前記支持構造体(252)の前記要素間にさらに気体または気体混合物が位置している、
請求項23記載のウェハ合成物。
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