JP7413022B2 - 表示パネル、その駆動方法、及び表示装置 - Google Patents
表示パネル、その駆動方法、及び表示装置 Download PDFInfo
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- JP7413022B2 JP7413022B2 JP2019568617A JP2019568617A JP7413022B2 JP 7413022 B2 JP7413022 B2 JP 7413022B2 JP 2019568617 A JP2019568617 A JP 2019568617A JP 2019568617 A JP2019568617 A JP 2019568617A JP 7413022 B2 JP7413022 B2 JP 7413022B2
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Description
本願は、2018年8月8日に出願された中国特許出願番号201810897353.4の優先権を主張し、そのすべての内容を参照によりここに援用する。
=1/2×K(Vtg-Vt1-Vth)2
=1/2×K(Vdata+Vth-V1-Vth)2
=1/2×K(Vdata-V1)2
Claims (18)
- 表示パネルであって、
第1の画素ユニットと第2の画素ユニットとを備える画素ユニット群と、第1の走査信号端子と第2の走査信号端子とを備える走査回路と、第1のデータ線と第2のデータ線と、を備え、
前記第1の画素ユニットと前記第2の画素ユニットとは、第1の画素回路と第2の画素回路とをそれぞれ備え、前記第1の画素回路は、第1のゲート制御端子と第1の発光制御端子とを備え、前記第2の画素回路は、第2のゲート制御端子と第2の発光制御端子とを備え、
前記第1の走査信号端子は、前記第1の画素ユニットと前記第2の画素ユニットとに同一のゲート信号を同時に供給するように構成され、及び/又は前記第2の走査信号端子は、前記第1の画素ユニットと前記第2の画素ユニットとに同一の発光制御信号を同時に供給するように構成され、
前記第1のデータ線は、前記第1の画素回路に接続され、前記第2のデータ線は、前記第2の画素回路に接続され、
前記表示パネルは、第1のサブ周期と第2のサブ周期とを順次含む第1の周期において、前記走査回路の第1の走査信号端を用いて前記第1のゲート制御端子と前記第2のゲート制御端子とに前記同一のゲート信号を同時に供給するように構成され、
前記第1のサブ周期において、前記第1のデータ線を介して前記第1の画素回路に第1のデータ信号を書き込み、前記第2のデータ線を介して前記第2の画素回路に第2のデータ信号を書き込むようにさらに構成され、
前記表示パネルは、前記第1のサブ周期において前記第1の画素回路に前記第1のデータ信号を書き込むように、第1の書き込み周期において前記第1のデータ線に前記第1のデータ信号を書き込むように構成され、
前記表示パネルは、前記第1のサブ周期において前記第2の画素回路に前記第2データ信号を書き込むように、第2の書き込み周期において前記第2のデータ線に前記第2のデータ信号を書き込むようにさらに構成され、
前記表示パネルは、前記第1の書き込み周期は、前記第1のサブ周期の前に設けられ、かつ第1のサブ周期と時間的に隣接し、前記第2の書き込み周期は、前記第1のサブ周期内に設けられ、あるいは前記第2の書き込み周期は、前記第1のサブ周期の前に設けられ、かつ前記第1のサブ周期と時間的に隣接し、前記第1の書き込み周期は、前記第2の書き込み周期の前に設けられ、かつ前記第2の書き込み周期と時間的に隣接している、表示パネル。 - 少なくとも1本のゲート線をさらに備え、
前記第1の走査信号端子は、前記少なくとも1本のゲート線を介して前記第1のゲート制御端子と前記第2のゲート制御端子とに接続され、前記少なくとも1本のゲート線を介して前記第1の画素ユニットと前記第2の画素ユニットとに前記同一のゲート信号を同時に供給する、請求項1に記載の表示パネル。 - 少なくとも1本の発光制御線をさらに備え、
前記第2の走査信号端子は、前記少なくとも1本の発光制御線を介して前記第1の発光制御端子と前記第2の発光制御端子とに接続され、前記第1の画素ユニットと前記第2の画素ユニットとに前記同一の発光制御信号を同時に供給する、請求項2に記載の表示パネル 。 - 多重化回路と、データ駆動回路とをさらに備え、
前記データ駆動回路は、第1のデータ信号出力端子を備え、前記多重化回路は、前記第1のデータ信号出力端子と、前記第1のデータ線と、前記第2のデータ線とに接続され、前記第1のデータ信号出力端子を前記第1のデータ線と前記第2のデータ線とに時分割的に電気的に接続するように構成される、請求項1に記載の表示パネル。 - 前記多重化回路は、第1の選択回路と、第2の選択回路とを備え、
前記第1の選択回路の第1の端子は前記第1のデータ線に接続され、前記第2の選択回路の第1の端子は前記第2のデータ線に接続され、前記第1の選択回路及び前記第2の選択回路の両方の第2の端子は前記第1のデータ信号出力端子に接続されている、請求項4に記載の表示パネル。 - 前記第1の選択回路は第1の多重化トランジスタを備え、前記第2の選択回路は第2の多重化トランジスタを備え、
前記第1の多重化トランジスタの第1の端子及び第2の端子は、前記第1の選択回路の前記第1の端子及び前記第2の端子としてそれぞれ構成され、前記第2の多重化トランジスタの第1の端子及び第2の端子は、前記第2の選択回路の前記第1の端子及び前記第2の端子としてそれぞれ構成される、請求項5に記載の表示パネル。 - 前記第1の多重化トランジスタの制御端子と前記第2の多重化トランジスタの制御端子は同一の多重化制御信号を受信するように構成される、請求項6に記載の表示パネル。
- 前記第1の多重化トランジスタと前記第2の多重化トランジスタとは逆の種類である、請求項7に記載の表示パネル。
- 前記第1の多重化トランジスタと前記第2の多重化トランジスタとは同一の種類である、請求項7に記載の表示パネル。
- 前記多重化回路は、インバータをさらに備え、前記インバータの一方の端子は前記第2の多重化トランジスタの前記制御端子に電気的に接続され、前記インバータの他方の端子は前記同一の多重化制御信号を受信するように構成される、請求項9に記載の表示パネル 。
- 前記第1の多重化トランジスタの制御端子と前記第2の多重化トランジスタの制御端子とは、互いに反転している第1の多重化制御信号及び第2の多重化制御信号をそれぞれ受信するように構成され、前記第1の多重化トランジスタと前記第2の多重化トランジスタとは同一の種類である、請求項6に記載の表示パネル。
- 前記多重化回路は、前記第1の多重化トランジスタ及び前記第2の多重化トランジスタの前記制御端子に前記同一の又は反転している多重化制御信号を供給するように構成された多重化信号発生回路をさらに備える、請求項7から11のいずれか1項に記載の表示パネル。
- 前記走査回路は、前記第1の走査信号端子を備える第1の走査サブ回路と、前記第2の走査信号端子を備える第2の走査サブ回路とを備える、請求項1から12のいずれか1項に記載の表示パネル。
- 前記第1の走査サブ回路は、カスケードされるように構成され、前記第1の走査信号端子を備える第1のシフトレジスタユニットを備え、前記第2の走査サブ回路は、カスケードされるように構成され、前記第2の走査信号端子を備える第2のシフトレジスタユニットを備える、請求項13に記載の表示パネル。
- 請求項1から14のいずれか1項に記載の表示パネルを備える、表示装置。
- 第1のサブ周期と第2のサブ周期とを順次含む第1の周期において、前記走査回路の前記第1の走査信号端子を用いて前記第1のゲート制御端子及び前記第2のゲート制御端子に前記ゲート信号を同時に供給することと、
前記第1のサブ周期において、前記第1のデータ線を介して前記第1の画素回路に第1のデータ信号を、前記第2のデータ線を介して前記第2の画素回路に第2のデータ信号を書き込むことと、を含む、請求項1から14のいずれか1項に記載の前記表示パネルの駆動方法。 - 第2の周期において、前記走査回路の前記第2の走査信号端子を用いて、前記第1の発光制御端子と前記第2の発光制御端子とに前記同一の発光制御信号を同時に供給することをさらに含む、請求項16に記載の表示パネルの駆動方法。
- 前記表示パネルは、多重化回路とデータ駆動回路とをさらに備え、前記データ駆動回路は第1のデータ信号出力端子を備え、前記表示パネルの駆動方法は、
前記第1の書き込み周期において前記第1のデータ信号出力端子に前記第1のデータ線を接続して、前記第1のデータ信号を前記第1のデータ線に書き込むことと、
前記第2の書き込み周期において前記第 1 のデータ信号出力端子に前記第2のデータ線を接続して、前記第2のデータ信号を前記第2のデータ線に書き込むことと、をさらに含む、請求項17に記載の表示パネルの駆動方法。
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