JP7352073B2 - 半導体装置、半導体装置の製造方法及び電子装置 - Google Patents
半導体装置、半導体装置の製造方法及び電子装置 Download PDFInfo
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- JP7352073B2 JP7352073B2 JP2019152859A JP2019152859A JP7352073B2 JP 7352073 B2 JP7352073 B2 JP 7352073B2 JP 2019152859 A JP2019152859 A JP 2019152859A JP 2019152859 A JP2019152859 A JP 2019152859A JP 7352073 B2 JP7352073 B2 JP 7352073B2
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L2924/181—Encapsulation
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- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
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- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
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- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
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Description
図1は第1の実施の形態に係る半導体装置の一例について説明する図である。図1には、半導体装置の一例の要部断面図を模式的に示している。
基板10には、各種半導体材料又は化合物半導体材料が用いられる。基板10に用いられる半導体材料としては、シリコン(Si)、ゲルマニウム(Ge)等が挙げられる。基板10に用いられる化合物半導体材料としては、GaN、ガリウムヒ素(GaAs)、インジウムリン(InP)、シリコンカーバイド(SiC)、シリコンゲルマニウム(SiGe)等が挙げられる。基板10は、各種半導体材料又は化合物半導体材料からなるもののほか、各種半導体材料又は化合物半導体材料の層が、別の基板や層の上に設けられたものであってもよい。
図2はダイヤモンド形成プロセスの一例について説明する図である。図2(A)には、ダイヤモンドの成長核生成工程の一例の要部断面図を模式的に示している。図2(B)には、ダイヤモンドの結晶成長工程の一例の要部断面図を模式的に示している。
図5は金属粒子の面密度について説明する図である。図5(A)には、金属粒子の面密度が比較的高い場合の一例の要部断面図を模式的に示している。図5(B)には、金属粒子の面密度が比較的低い場合の一例の要部断面図を模式的に示している。また、図6は金属粒子の粒径について説明する図である。図6(A)には、金属粒子の粒径が比較的小さい場合の一例の要部断面図を模式的に示している。図6(B)には、金属粒子の粒径が比較的大きい場合の一例の要部断面図を模式的に示している。
基板10で発生する熱2を、ダイヤモンド層40を用いて放熱するためには、ダイヤモンド層40或いはその結晶成長初期層の熱伝導率が、基板10との間に設けられる絶縁層20の熱伝導率よりも大きいことを要する。絶縁層20に用いられる絶縁材料の熱伝導率、及び絶縁層20とダイヤモンド層40の結晶成長初期層との間の熱伝導シミュレーションから、結晶成長初期層の熱伝導率が10W/m・Kよりも大きいと、一定以上の放熱効果が得られることが見出された。例えば、上記図4より、ダイヤモンド粒子43の粒径が10nm以上であるときのダイヤモンド層40の熱伝導率は、10W/m・Kを上回る、およそ20W/m・Kである。粒径が10nm以上のダイヤモンド粒子43が絶縁層20の表面20aに設けられる場合、結晶成長の起点となるダイヤモンド核41の隣接するもの同士の間の距離は10nm以上となる。これを、絶縁層20の表面20aにおけるダイヤモンド核41の面密度に換算すると、1×1012cm-2以下となる。1つの金属粒子30上に1つのダイヤモンド核41が生成され、それを起点にダイヤモンド粒子43が結晶成長されるとすると(図2(A))、ダイヤモンド核41の面密度は、金属粒子30の面密度に等しくなる。従って、ダイヤモンド粒子43の粒径を10nm以上とする場合、絶縁層20の表面20aにおける金属粒子30の面密度は、1×1012cm-2以下に設定される。
続いて、金属粒子30の粒径について述べる。
尚、ここで述べた金属粒子30の面密度及び粒径の範囲は一例であって、上記の範囲に限定されるものではない。例えば、半導体素子11又はそれを備える基板10の発熱量に基づき、ダイヤモンド層40の熱伝導率を設定し、ダイヤモンド粒子43の粒径を設定し、そこからダイヤモンド核41の面密度を設定する。或いは、基板10上に形成するダイヤモンド層40の厚さに基づき、ダイヤモンド粒子43の粒径を設定し、そこからダイヤモンド核41の面密度を設定する。そして、設定されたダイヤモンド核41の面密度から、金属粒子30の面密度の範囲を設定する。また、金属粒子30に用いられる金属材料の、ダイヤモンド核41の生成され易さ、絶縁層20に対するダイヤモンド核41の生成され易さ、或いは、ダイヤモンド核41を生成させる際の生成条件等に基づき、金属粒子30の範囲を設定する。
ここでは、上記第1の実施の形態で述べたような手法を、窒化物半導体を用いた半導体デバイスの1つであるHEMTに適用する例を、第2の実施の形態として説明する。
図7に示す半導体装置100は、上記のようなHEMTの一例である。この半導体装置100は、基板110、バッファ層120、チャネル層130、バリア層140、ゲート電極150、ソース電極160及びドレイン電極170を含む構造体101を備える。この構造体101には、絶縁層180が含まれてよい。半導体装置100は更に、構造体101上に設けられた絶縁層220、金属粒子230及びダイヤモンド層240を備える。
バッファ層120は、基板110上に設けられる。バッファ層120には、窒化物半導体、例えば、アルミニウムガリウムナイトライド(AlGaN)が用いられる。例えば、基板110上に初期層として設けられた、図示しないアルミニウムナイトライド(AlN)層上に、AlGaNを用いてバッファ層120が設けられる。バッファ層120(及びその初期層)は、有機金属気相成長(Metal Organic Chemical Vapor Deposition;MOCVD、又はMetal Organic Vapor Phase Epitaxy;MOVPE)法、又は分子線エピタキシー(Molecular Beam Epitaxy;MBE)法を用いて、基板110上に形成される。
図8及び図9は第2の実施の形態に係る半導体装置の形成方法の一例について説明する図である。図8(A)~図8(C)及び図9(A)~図9(C)にはそれぞれ、半導体装置の形成工程の一例の要部断面図を模式的に示している。
各層の結晶成長後、図8(B)に示すように、バリア層140の一部が除去され、チャネル層130に接続されるソース電極160及びドレイン電極170が形成される。その際は、まず、フォトリソグラフィ技術及びエッチング技術を用いて、ソース電極160及びドレイン電極170を形成する領域のバリア層140が除去される。次いで、フォトリソグラフィ技術、蒸着技術及びリフトオフ技術を用いて、ソース電極160及びドレイン電極170を形成する領域の、バリア層140が除去されたチャネル層130上に、電極用金属、例えば、TaとAlとの積層体が形成される。その後、例えば、窒素(N2)等の不活性ガス雰囲気中で熱処理が行われ、電極用金属がオーミック接続される。これにより、チャネル層130上に、オーミック電極として機能するソース電極160及びドレイン電極170が形成される。
尚、ここでは、チャネル層130に単層構造のGaNを用い、バリア層140に単層構造のAlGaNを用いる例を示したが、チャネル層130及びバリア層140の構造は、この例に限定されるものではない。例えば、チャネル層130には、InGaN、AlGaN、InAlGaN等の窒化物半導体が用いられてもよく、1種の窒化物半導体の単層構造が用いられてもよいし、1種又は2種以上の窒化物半導体の積層構造が用いられてもよい。また、バリア層140には、InAlN、InAlGaN、AlN等の窒化物半導体が用いられてもよく、1種の窒化物半導体の単層構造が用いられてもよいし、1種又は2種以上の窒化物半導体の積層構造が用いられてもよい。
図10(A)は、図9(A)の工程における、金属層231が形成される前の絶縁層220の原子間力顕微鏡(Atomic Force Microscope;AFM)像のイメージ図である。図10(B)は、図9(A)の工程における、絶縁層220上に形成された金属層231のAFM像のイメージ図である。図10(C)は、図9(B)の工程における、金属層231の熱処理を行った後のAFM像のイメージ図である。
図11(A)は、金属粒子230が形成されていない絶縁層220のAFM像のイメージ図である。図11(B)は、金属粒子230が形成されていない絶縁層220上にダイヤモンド層240が結晶成長された時(結晶成長初期層)のAFM像のイメージ図である。また、図12(A)は、金属粒子230が形成された絶縁層220のAFM像のイメージ図であって、上記図10(C)に示した、金属層231の熱処理を行った後のAFM像のイメージ図に相当するものである。図12(B)は、金属粒子230が形成された絶縁層220上にダイヤモンド層240が結晶成長された時(結晶成長初期層)のAFM像のイメージ図である。
図13は第3の実施の形態に係る半導体装置の一例について説明する図である。図13には、半導体装置の一例の要部断面図を模式的に示している。
図15は第4の実施の形態に係る半導体装置の一例について説明する図である。図15には、半導体装置の一例の要部断面図を模式的に示している。
図16及び図17は第4の実施の形態に係る半導体装置の形成方法の一例について説明する図である。図16(A)~図16(C)並びに図17(A)及び図17(B)にはそれぞれ、半導体装置の形成工程の一例の要部断面図を模式的に示している。
尚、ここでは、ゲート電極150を形成した後に(図16(B))、ダイヤモンド層240を形成する例を示した(図16(C))。このほか、金属粒子230が設けられた絶縁層220上に、ゲート電極150を形成せずにダイヤモンド層240を形成し、ダイヤモンド層240の形成後に、エッチング技術等を用いてバリア層140に通じる開口部を形成し、そこにゲート電極150を形成してもよい。
図18は第5の実施の形態に係る半導体装置の一例について説明する図である。図18には、半導体装置の一例の要部断面図を模式的に示している。
図19は第6の実施の形態に係る半導体装置の一例について説明する図である。図19には、半導体装置の一例の要部断面図を模式的に示している。
図20は第7の実施の形態に係る半導体装置の一例について説明する図である。図20には、半導体装置の一例の要部断面図を模式的に示している。
ここでは、上記のような構成を有する半導体装置の、半導体パッケージへの適用例を、第8の実施の形態として説明する。
図21に示す半導体パッケージ300は、ディスクリートパッケージの一例である。半導体パッケージ300は、例えば、上記第2の実施の形態で述べた半導体装置100、半導体装置100が搭載されたリードフレーム310、及びそれらを封止する樹脂320を含む。
ここでは、上記のような構成を有する半導体装置の、力率改善回路への適用例を、第9の実施の形態として説明する。
図22に示す力率改善(Power Factor Correction;PFC)回路400は、スイッチ素子410、ダイオード420、チョークコイル430、コンデンサ440、コンデンサ450、ダイオードブリッジ460及び交流電源470(AC)を含む。
ここでは、上記のような構成を有する半導体装置の、電源装置への適用例を、第10の実施の形態として説明する。
図23に示す電源装置500は、高圧の一次側回路510及び低圧の二次側回路520、並びに一次側回路510と二次側回路520との間に設けられるトランス530を含む。一次側回路510には、上記第9の実施の形態で述べたようなPFC回路400、及びPFC回路400のコンデンサ450の両端子間に接続されたインバータ回路、例えば、フルブリッジインバータ回路540が含まれる。フルブリッジインバータ回路540には、複数(ここでは一例として4つ)のスイッチ素子541、スイッチ素子542、スイッチ素子543及びスイッチ素子544が含まれる。二次側回路520には、複数(ここでは一例として3つ)のスイッチ素子521、スイッチ素子522及びスイッチ素子523が含まれる。
ここでは、上記のような構成を有する半導体装置の、増幅器への適用例を、第11の実施の形態として説明する。
図24に示す増幅器600は、ディジタルプレディストーション回路610、ミキサー620、ミキサー630及びパワーアンプ640を含む。
2 熱
10,110 基板
10a,20a,110a,220a 表面
11 半導体素子
20,180,220 絶縁層
30,230 金属粒子
40,40A,240,250 ダイヤモンド層
41 ダイヤモンド核
42 ダイヤモンド結晶
43,43A,243 ダイヤモンド粒子
101,102 構造体
110b 裏面
120 バッファ層
130 チャネル層
131a,131b 凹部
140 バリア層
150 ゲート電極
150a,160a,170a パッド
160 ソース電極
161,171 コンタクト層
170 ドレイン電極
181,221 開口部
200 2DEG
225 絶縁層原料ガス
231 金属層
235 金属粒子原料ガス
260 カソード電極
270 アノード電極
300 半導体パッケージ
310 リードフレーム
310a ダイパッド
311 ゲートリード
312 ソースリード
313 ドレインリード
320 樹脂
330 ワイヤ
400 PFC回路
410,521,522,523,541,542,543,544 スイッチ素子
420 ダイオード
430 チョークコイル
440,450 コンデンサ
460 ダイオードブリッジ
470 交流電源
500 電源装置
510 一次側回路
520 二次側回路
530 トランス
540 フルブリッジインバータ回路
600 増幅器
610 ディジタルプレディストーション回路
620,630 ミキサー
640 パワーアンプ
Claims (9)
- 基板と、
前記基板に設けられ、シリコンを含有する絶縁層と、
前記絶縁層の表面に分散して設けられた第1金属粒子群と、
前記絶縁層の内部に設けられた第2金属粒子と、
前記表面に設けられた第1ダイヤモンド層と
を含むことを特徴とする半導体装置。 - 前記第1金属粒子群の前記表面における面密度は、1×104cm-2以上であって且つ1×1012cm-2以下であることを特徴とする請求項1に記載の半導体装置。
- 前記第1金属粒子群の粒径は、2nm以上であって且つ1μm以下であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記第1金属粒子群は、イリジウム、白金、ニッケル、モリブデン、タングステン、銅及び金のうちの1種又は2種以上を含むことを特徴とする請求項1乃至3のいずれかに記載の半導体装置。
- 前記第1ダイヤモンド層は、前記表面の、前記第1金属粒子群が設けられた各々の位置に、結晶粒を有することを特徴とする請求項1乃至4のいずれかに記載の半導体装置。
- 前記基板は、
第1窒化物半導体を含有するチャネル層と、
前記チャネル層に積層され、第2窒化物半導体を含有するバリア層と、
前記バリア層の、前記チャネル層とは反対の側に設けられるゲート電極と、
前記チャネル層の、前記ゲート電極が設けられる側にあって前記ゲート電極を挟むように設けられるソース電極及びドレイン電極と
を含み、
前記基板の、前記ゲート電極、前記ソース電極及び前記ドレイン電極が設けられる側に、前記絶縁層が設けられることを特徴とする請求項1乃至5のいずれかに記載の半導体装置。 - 前記基板の、前記第1ダイヤモンド層とは反対の側に設けられた第2ダイヤモンド層を含むことを特徴とする請求項1乃至6のいずれかに記載の半導体装置。
- 基板に、シリコンを含有する絶縁層を形成する工程と、
前記絶縁層の表面に第1金属粒子群を分散させて形成する工程と、
前記絶縁層の内部に第2金属粒子を形成する工程と、
前記表面に第1ダイヤモンド層を形成する工程と
を含むことを特徴とする半導体装置の製造方法。 - 基板と、
前記基板に設けられ、シリコンを含有する絶縁層と、
前記絶縁層の表面に分散して設けられた第1金属粒子群と、
前記絶縁層の内部に設けられた第2金属粒子と、
前記表面に設けられた第1ダイヤモンド層と
を含む半導体装置を備えることを特徴とする電子装置。
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JPH05347299A (ja) * | 1992-06-15 | 1993-12-27 | Seiko Epson Corp | 半導体装置 |
JP3226367B2 (ja) * | 1993-03-05 | 2001-11-05 | 日本特殊陶業株式会社 | ダイヤモンドの選択形成方法 |
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