JP7250641B2 - アライメント装置及び半導体装置の製造方法 - Google Patents

アライメント装置及び半導体装置の製造方法 Download PDF

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JP7250641B2
JP7250641B2 JP2019144962A JP2019144962A JP7250641B2 JP 7250641 B2 JP7250641 B2 JP 7250641B2 JP 2019144962 A JP2019144962 A JP 2019144962A JP 2019144962 A JP2019144962 A JP 2019144962A JP 7250641 B2 JP7250641 B2 JP 7250641B2
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alignment
pitch
patterns
semiconductor
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JP2021027208A5 (enExample
JP2021027208A (ja
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未希 遠島
統 山根
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Kioxia Corp
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Kioxia Corp
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Priority to US16/810,945 priority patent/US11387131B2/en
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    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
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    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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  • Condensed Matter Physics & Semiconductors (AREA)
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JP2019144962A 2019-08-06 2019-08-06 アライメント装置及び半導体装置の製造方法 Active JP7250641B2 (ja)

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JP2019144962A JP7250641B2 (ja) 2019-08-06 2019-08-06 アライメント装置及び半導体装置の製造方法
US16/810,945 US11387131B2 (en) 2019-08-06 2020-03-06 Alignment apparatus and method of manufacturing semiconductor device

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JP2019144962A JP7250641B2 (ja) 2019-08-06 2019-08-06 アライメント装置及び半導体装置の製造方法

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US11688717B2 (en) * 2021-08-26 2023-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanical wafer alignment detection for bonding process
KR20230053148A (ko) * 2021-10-14 2023-04-21 삼성전자주식회사 반도체 칩 및 반도체 패키지
US12363941B2 (en) * 2022-02-28 2025-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. GAA LDMOS structure for HV operation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267682A (ja) 2009-05-12 2010-11-25 Bondtech Inc アライメント装置、アライメント方法および半導体装置
JP2014168089A (ja) 2014-04-23 2014-09-11 Nikon Corp 基板重ね合わせ装置、基板重ね合わせ方法、及びデバイスの製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002032031A (ja) * 2000-05-12 2002-01-31 Seiko Epson Corp 電気光学装置の製造方法、端子の接続方法、電気光学装置および電子機器
TW526573B (en) 2000-12-27 2003-04-01 Koninkl Philips Electronics Nv Method of measuring overlay
JP5369588B2 (ja) 2008-10-01 2013-12-18 株式会社ニコン 接合評価方法、接合評価装置、基板貼り合わせ装置、評価ゲージおよび積層型半導体装置
JP2011159908A (ja) 2010-02-03 2011-08-18 Sony Corp 薄膜トランジスタおよびその製造方法、並びに表示装置
KR101741384B1 (ko) * 2013-12-06 2017-05-29 에베 그룹 에. 탈너 게엠베하 기질들을 정렬하기 위한 장치 및 방법
KR102537289B1 (ko) * 2016-07-12 2023-05-30 가부시키가이샤 니콘 적층 기판 제조 방법, 적층 기판 제조 장치, 적층 기판 제조 시스템, 및 기판 처리 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010267682A (ja) 2009-05-12 2010-11-25 Bondtech Inc アライメント装置、アライメント方法および半導体装置
JP2014168089A (ja) 2014-04-23 2014-09-11 Nikon Corp 基板重ね合わせ装置、基板重ね合わせ方法、及びデバイスの製造方法

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