JP7248493B2 - 部品内蔵基板及びその製造方法 - Google Patents
部品内蔵基板及びその製造方法 Download PDFInfo
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- JP7248493B2 JP7248493B2 JP2019085376A JP2019085376A JP7248493B2 JP 7248493 B2 JP7248493 B2 JP 7248493B2 JP 2019085376 A JP2019085376 A JP 2019085376A JP 2019085376 A JP2019085376 A JP 2019085376A JP 7248493 B2 JP7248493 B2 JP 7248493B2
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- wiring layer
- insulating layer
- layer
- cavity
- electronic component
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Description
第1の実施形態について説明する。第1の実施形態は部品内蔵基板に関する。
まず、部品内蔵基板の構造について説明する。図1は、第1の実施形態に係る部品内蔵基板の構造を示す断面図である。図2は、基準パターンが形成された配線層の構成を示す図である。図2は、図1中の2点鎖線で囲んだ領域19a内の構成を示す。
ここで、基準パターン110a、110b、110c、110d、120a、120b、120c及び120dについて詳細に説明する。
次に、基準パターン110a、110b、110c、110d、120a、120b、120c及び120dに含まれるスリットについて説明する。ここでは、まず、代表として、図3を参照しながら、基準パターン110c及び120cに含まれるスリットについて説明する。図3は、基準パターン110c及び120cに含まれるスリットを示す図である。図3は、図2中の2点鎖線で囲んだ領域19b内の構成を示す。基準パターン110a、110b、110c、110d、120a、120b、120c及び120dに含まれるスリットは目盛りの一例である。
次に、第1の実施形態に係る部品内蔵基板10の製造方法について説明する。図5~図17は、第1の実施形態に係る部品内蔵基板10の製造方法を示す断面図である。図18~図21は、第1の実施形態に係る部品内蔵基板10の製造方法における基準パターンの露出状態の変化を示す図である。
次に、第2の実施形態について説明する。第2の実施形態は、部品内蔵基板10及び半導体チップを含む半導体パッケージに関する。図27は、第2の実施形態に係る半導体パッケージを示す断面図である。
次に、種々の変形例について説明する。
15 キャビティ
20 半導体パッケージ
23 配線層(第1の配線層)
24 絶縁層(第1の絶縁層)
25 配線層(第2の配線層)
25x 開口パターン
26 絶縁層(第2の絶縁層)
60 電子部品
110a~110d、120a~120d 基準パターン
111、112、121、122 スリット
115 キャビティ形成領域
115A~115D、160A~160D 辺
160 部品搭載領域
Claims (11)
- 基準パターンを備えた第1の配線層と、
前記第1の配線層上に形成された第1の絶縁層と、
前記第1の絶縁層に形成されたキャビティ内で、前記第1の配線層上に搭載された電子部品と、
を有し、
前記基準パターンは、目盛りとして、前記第1の配線層を貫通する複数のスリットを有し、
前記基準パターンは、
平面視で前記電子部品の側面と交差する第1の部分と、
平面視で前記キャビティの側面と交差する第2の部分と、
を有することを特徴とする部品内蔵基板。 - 前記第1の絶縁層上に形成された第2の配線層と、
前記第2の配線層上に形成された第2の絶縁層と、
を有し、
前記キャビティは、前記第2の配線層及び前記第2の絶縁層に繋がるように形成され、
前記キャビティ内において、前記第2の配線層の少なくとも一部の上面が前記第2の絶縁層から露出していることを特徴とする請求項1に記載の部品内蔵基板。 - 前記基準パターンは、前記電子部品の互いに0度超の角度で交わる2側面に対応するように設けられていることを特徴とする請求項2に記載の部品内蔵基板。
- 前記電子部品は、多角形の平面形状を有し、
前記基準パターンは、前記多角形の少なくとも2辺に対応して、複数設けられていることを特徴とする請求項1乃至3のいずれか1項に記載の部品内蔵基板。 - 前記基準パターンは、前記第1の部分及び前記第2の部分を複数ずつ有することを特徴とする請求項1乃至4のいずれか1項に記載の部品内蔵基板。
- 前記複数のスリットは、平面視で、前記電子部品の前記側面に平行な方向から傾斜した方向に一定の間隔で配列していることを特徴とする請求項1乃至5のいずれか1項に記載の部品内蔵基板。
- 前記複数のスリットは、
第1の平面形状の複数の第1のスリットと、
前記第1の平面形状とは異なる第2の平面形状の複数の第2のスリットと、
を含み、
前記第2のスリットは、一定数の前記第1のスリットの群毎に設けられていることを特徴とする請求項6に記載の部品内蔵基板。 - 基準パターンを備えた第1の配線層を形成する工程と、
前記第1の配線層上に第1の絶縁層を形成する工程と、
前記第1の絶縁層にキャビティを形成する工程と、
前記キャビティ内で、前記第1の配線層上に電子部品を搭載する工程と、
を有し、
前記基準パターンは、
平面視で前記電子部品の側面と交差する第1の部分と、
平面視で前記キャビティの側面と交差する第2の部分と、
を有し、
前記電子部品を搭載する工程の後に、前記第1の部分及び前記第2の部分のうち前記キャビティ内に露出している部分の前記基準パターンに基づいて前記電子部品と前記キャビティとの間の位置精度を確認する工程を有することを特徴とする部品内蔵基板の製造方法。 - 前記第1の絶縁層を形成する工程と前記キャビティを形成する工程との間に、
前記第1の絶縁層上に第2の配線層を形成する工程と、
前記第2の配線層上に第2の絶縁層を形成する工程と、
を有し、
前記キャビティは、前記第2の配線層及び前記第2の絶縁層に繋がり、前記キャビティ内において、前記第2の配線層の少なくとも一部の上面が前記第2の絶縁層から露出するように形成することを特徴とする請求項8に記載の部品内蔵基板の製造方法。 - 基準パターンを備えた第1の配線層を形成する工程と、
前記第1の配線層上に第1の絶縁層を形成する工程と、
前記第1の絶縁層にキャビティを形成する工程と、
前記キャビティ内で、前記第1の配線層上に電子部品を搭載する工程と、
を有し、
前記基準パターンは、
平面視で前記電子部品の側面と交差する第1の部分と、
平面視で前記キャビティの側面と交差する第2の部分と、
を有し、
前記基準パターンが目盛りを有し、
前記目盛りとして、前記第1の配線層を貫通する複数のスリットを形成する工程を有することを特徴とする部品内蔵基板の製造方法。 - 前記複数のスリットを、平面視で、前記電子部品の前記側面に平行な方向から傾斜した方向に一定の間隔で配列させる工程を有することを特徴とする請求項10に記載の部品内蔵基板の製造方法。
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