JP7159059B2 - 積層基板及び積層基板製造方法 - Google Patents

積層基板及び積層基板製造方法 Download PDF

Info

Publication number
JP7159059B2
JP7159059B2 JP2019002179A JP2019002179A JP7159059B2 JP 7159059 B2 JP7159059 B2 JP 7159059B2 JP 2019002179 A JP2019002179 A JP 2019002179A JP 2019002179 A JP2019002179 A JP 2019002179A JP 7159059 B2 JP7159059 B2 JP 7159059B2
Authority
JP
Japan
Prior art keywords
insulating layer
layer
conductor
insulating material
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019002179A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020113609A5 (https=
JP2020113609A (ja
Inventor
美沙紀 小松
克哉 深瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2019002179A priority Critical patent/JP7159059B2/ja
Priority to US16/728,051 priority patent/US11289403B2/en
Publication of JP2020113609A publication Critical patent/JP2020113609A/ja
Publication of JP2020113609A5 publication Critical patent/JP2020113609A5/ja
Application granted granted Critical
Publication of JP7159059B2 publication Critical patent/JP7159059B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2072—Anchoring, i.e. one structure gripping into another
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
JP2019002179A 2019-01-09 2019-01-09 積層基板及び積層基板製造方法 Active JP7159059B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2019002179A JP7159059B2 (ja) 2019-01-09 2019-01-09 積層基板及び積層基板製造方法
US16/728,051 US11289403B2 (en) 2019-01-09 2019-12-27 Multi-layer substrate and method for manufacturing multi-layer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019002179A JP7159059B2 (ja) 2019-01-09 2019-01-09 積層基板及び積層基板製造方法

Publications (3)

Publication Number Publication Date
JP2020113609A JP2020113609A (ja) 2020-07-27
JP2020113609A5 JP2020113609A5 (https=) 2021-12-09
JP7159059B2 true JP7159059B2 (ja) 2022-10-24

Family

ID=71404448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019002179A Active JP7159059B2 (ja) 2019-01-09 2019-01-09 積層基板及び積層基板製造方法

Country Status (2)

Country Link
US (1) US11289403B2 (https=)
JP (1) JP7159059B2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019013544A (ja) * 2017-07-07 2019-01-31 株式会社三洋物産 遊技機
JP2019013543A (ja) * 2017-07-07 2019-01-31 株式会社三洋物産 遊技機
US11171084B2 (en) * 2020-04-06 2021-11-09 International Business Machines Corporation Top via with next level line selective growth
KR102845137B1 (ko) * 2020-10-07 2025-08-12 삼성전자주식회사 안테나를 포함하는 전자 장치
JP2023111532A (ja) * 2022-01-31 2023-08-10 株式会社アイシン 半導体装置および半導体装置の製造方法
WO2024135456A1 (ja) * 2022-12-20 2024-06-27 京セラ株式会社 配線基板およびその製造方法
JP2024167847A (ja) * 2023-05-22 2024-12-04 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
WO2025069676A1 (ja) * 2023-09-29 2025-04-03 株式会社村田製作所 コンデンサ素子

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005322659A (ja) 2004-05-06 2005-11-17 Matsushita Electric Ind Co Ltd 配線基板およびその製造方法ならびに半導体装置
JP2013229525A (ja) 2012-04-26 2013-11-07 Ngk Spark Plug Co Ltd 多層配線基板
US20170188458A1 (en) 2015-12-28 2017-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the Pad for Bonding Integrated Passive Device in InFO Package

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4245215B2 (ja) 1997-12-29 2009-03-25 イビデン株式会社 多層プリント配線板
US6313026B1 (en) * 2000-04-10 2001-11-06 Micron Technology, Inc. Microelectronic contacts and methods for producing same
WO2003071843A1 (en) * 2002-02-22 2003-08-28 Fujikura Ltd. Multilayer wiring board, base for multilayer wiring board, printed wiring board, and its manufacturing method
US20050081376A1 (en) * 2003-10-21 2005-04-21 Sir Jiun H. Robust interlocking via
JP2006093465A (ja) * 2004-09-24 2006-04-06 Toshiba Corp 樹脂封止型電子装置およびその製造方法
US7446036B1 (en) * 2007-12-18 2008-11-04 International Business Machines Corporation Gap free anchored conductor and dielectric structure and method for fabrication thereof
JP2018017987A (ja) * 2016-07-29 2018-02-01 株式会社ジャパンディスプレイ 表示装置
JP6762793B2 (ja) * 2016-07-29 2020-09-30 株式会社ジャパンディスプレイ 電子機器及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005322659A (ja) 2004-05-06 2005-11-17 Matsushita Electric Ind Co Ltd 配線基板およびその製造方法ならびに半導体装置
JP2013229525A (ja) 2012-04-26 2013-11-07 Ngk Spark Plug Co Ltd 多層配線基板
US20170188458A1 (en) 2015-12-28 2017-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the Pad for Bonding Integrated Passive Device in InFO Package
CN106952885A (zh) 2015-12-28 2017-07-14 台湾积体电路制造股份有限公司 封装件

Also Published As

Publication number Publication date
JP2020113609A (ja) 2020-07-27
US20200219794A1 (en) 2020-07-09
US11289403B2 (en) 2022-03-29

Similar Documents

Publication Publication Date Title
JP7159059B2 (ja) 積層基板及び積層基板製造方法
US9893016B2 (en) Multilayer wiring board having wiring structure for mounting multiple electronic components and method for manufacturing the same
JP4767269B2 (ja) 印刷回路基板の製造方法
JP5272090B2 (ja) 配線板とその製造方法
JP5512562B2 (ja) 多層配線基板
KR101025524B1 (ko) 배선 기판 및 그 제조 방법
US9756735B2 (en) Method for manufacturing printed wiring board
US20150014020A1 (en) Wiring substrate and method for manufacturing the same
KR102268388B1 (ko) 인쇄회로기판 및 그 제조방법
JP2009099619A (ja) コア基板およびその製造方法
JP7148278B2 (ja) 配線基板及びその製造方法
JP6189592B2 (ja) 部品組込み型印刷回路基板及びその製造方法
KR101233047B1 (ko) 빌드업 기판
KR101044787B1 (ko) 인쇄회로기판 제조방법
JP2008311612A (ja) 多層プリント基板およびその製造方法
KR20140048564A (ko) 코어기판, 그의 제조방법 및 메탈 비아용 구조체
JP2019047063A (ja) プリント配線板およびその製造方法
JP2014150091A (ja) 配線基板およびその製造方法
JP2022119655A (ja) 配線基板
JP4497548B2 (ja) 配線基板
JP2012160559A (ja) 配線基板の製造方法
JP4282161B2 (ja) 多層プリント配線板及び多層プリント配線板の製造方法
JP5565953B2 (ja) 配線基板およびその製造方法
TWI921489B (zh) 電路基板之製造方法
JP2024147936A (ja) 配線基板及び配線基板の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211029

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211029

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220912

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220927

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20221012

R150 Certificate of patent or registration of utility model

Ref document number: 7159059

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150