JP7118928B2 - 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善 - Google Patents

半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善 Download PDF

Info

Publication number
JP7118928B2
JP7118928B2 JP2019143000A JP2019143000A JP7118928B2 JP 7118928 B2 JP7118928 B2 JP 7118928B2 JP 2019143000 A JP2019143000 A JP 2019143000A JP 2019143000 A JP2019143000 A JP 2019143000A JP 7118928 B2 JP7118928 B2 JP 7118928B2
Authority
JP
Japan
Prior art keywords
wafer
semiconductor wafer
distortion
pattern
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019143000A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020021076A5 (https=
JP2020021076A (ja
Inventor
ホーゲ ジョシュア
イプ ネイサン
エストレラ ジョエル
デヴィリアーズ アントン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2020021076A publication Critical patent/JP2020021076A/ja
Publication of JP2020021076A5 publication Critical patent/JP2020021076A5/ja
Application granted granted Critical
Publication of JP7118928B2 publication Critical patent/JP7118928B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/238Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00Image enhancement or restoration
    • G06T5/80Geometric correction
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70525Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605Workpiece metrology
    • G03F7/70616Monitoring the printed patterns
    • G03F7/70625Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605Workpiece metrology
    • G03F7/70616Monitoring the printed patterns
    • G03F7/70633Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605Workpiece metrology
    • G03F7/706835Metrology information management or control
    • G03F7/706837Data analysis, e.g. filtering, weighting, flyer removal, fingerprints or root cause analysis
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691Handling of masks or workpieces
    • G03F7/70783Handling stress or warp of chucks, masks or workpieces, e.g. to compensate for imaging errors or considerations related to warpage of masks or workpieces due to their own weight
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • G06F30/23Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0431Apparatus for thermal treatment
    • H10P72/0436Apparatus for thermal treatment mainly by radiation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04Apparatus for manufacture or treatment
    • H10P72/0448Apparatus for applying a liquid, a resin, an ink or the like
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0616Monitoring of warpages, curvatures, damages, defects or the like
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7614Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27Structural arrangements therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27Structural arrangements therefor
    • H10P74/273Interconnections for measuring or testing, e.g. probe pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041Photolithographic processes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00Indexing scheme for image analysis or image enhancement
    • G06T2207/30Subject of image; Context of image processing
    • G06T2207/30108Industrial image inspection
    • G06T2207/30148Semiconductor; IC; Wafer
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00Image analysis
    • G06T7/0002Inspection of images, e.g. flaw detection
    • G06T7/0004Industrial image inspection

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2019143000A 2018-08-03 2019-08-02 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善 Active JP7118928B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/054,725 US10622233B2 (en) 2016-09-05 2018-08-03 Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer
US16/054725 2018-08-03

Publications (3)

Publication Number Publication Date
JP2020021076A JP2020021076A (ja) 2020-02-06
JP2020021076A5 JP2020021076A5 (https=) 2021-10-21
JP7118928B2 true JP7118928B2 (ja) 2022-08-16

Family

ID=69487426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019143000A Active JP7118928B2 (ja) 2018-08-03 2019-08-02 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善

Country Status (5)

Country Link
US (1) US10622233B2 (https=)
JP (1) JP7118928B2 (https=)
KR (1) KR102558635B1 (https=)
CN (1) CN110807273B (https=)
TW (1) TWI790391B (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3457213A1 (en) * 2017-09-18 2019-03-20 ASML Netherlands B.V. Methods and apparatus for use in a device manufacturing method
US10847419B2 (en) * 2018-03-14 2020-11-24 Raytheon Company Stress compensation and relief in bonded wafers
CN112585540B (zh) * 2018-08-22 2024-09-17 Asml荷兰有限公司 量测设备
US11393118B2 (en) 2019-06-18 2022-07-19 Kla Corporation Metrics for asymmetric wafer shape characterization
US11879170B2 (en) 2019-08-14 2024-01-23 Massachusetts Institute Of Technology Stress patterning systems and methods for manufacturing free-form deformations in thin substrates
KR20220167387A (ko) 2020-05-14 2022-12-20 에이에스엠엘 네델란즈 비.브이. 제품 피쳐에 대한 분해능상 계측을 사용하는 웨이퍼 정렬 방법
US12276922B2 (en) 2020-05-22 2025-04-15 Tokyo Electron Limited Backside deposition tuning of stress to control wafer bow in semiconductor processing
US11637043B2 (en) 2020-11-03 2023-04-25 Applied Materials, Inc. Analyzing in-plane distortion
US11829077B2 (en) * 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
JP7611274B2 (ja) * 2021-02-03 2025-01-09 東京エレクトロン株式会社 膜厚分析方法、膜厚分析装置及び記憶媒体
TWI889613B (zh) * 2021-04-27 2025-07-01 美商應用材料股份有限公司 用於半導體處理的應力與覆蓋管理
US12469725B2 (en) 2021-06-27 2025-11-11 Delta Design, Inc. Method for determining corrective film pattern to reduce semiconductor wafer bow
US12394618B2 (en) 2021-07-08 2025-08-19 Tokyo Electron Limited Method of adjusting wafer shape using multi-directional actuation films
US12051608B2 (en) * 2021-07-20 2024-07-30 Changxin Memory Technologies, Inc. Method for adjusting wafer deformation and semiconductor structure
US11782411B2 (en) * 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
KR20230048952A (ko) * 2021-10-05 2023-04-12 삼성전자주식회사 풀-칩 레이아웃을 이용한 레이아웃 검증 시스템 및 이를 이용한 레이아웃 검증 방법
US12001147B2 (en) 2021-11-19 2024-06-04 Tokyo Electron Limited Precision multi-axis photolithography alignment correction using stressor film
US20250028254A1 (en) * 2021-12-06 2025-01-23 Asml Netherlands B.V. Methods of determining a mechanical property of a layer applied to a substrate, and associated devices
EP4202551A1 (en) * 2021-12-23 2023-06-28 ASML Netherlands B.V. Methods of determining a mechanical property of a layer applied to a substrate, and associated devices
WO2023108530A1 (en) * 2021-12-16 2023-06-22 Yangtze Memory Technologies Co., Ltd. Prediction of wafer flatness
US11994807B2 (en) 2022-05-03 2024-05-28 Tokyo Electron Limited In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
KR20250008925A (ko) * 2022-05-13 2025-01-16 어플라이드 머티어리얼스, 인코포레이티드 개선된 분해능을 갖는 기판 곡률 제어용 도즈 매핑 및 기판 회전
JP2025516535A (ja) * 2022-05-13 2025-05-30 アプライド マテリアルズ インコーポレイテッド 基板曲率を使用して面外歪みを補償するためのドーズマッピング
US20240103385A1 (en) * 2022-09-28 2024-03-28 Applied Materials, Inc. Frequency and Amplitude Modulation of Implant Dose for Stress Management
US20250028294A1 (en) * 2023-07-18 2025-01-23 Applied Materials, Inc. Measurement of inherent substrate distortion
US20250216188A1 (en) * 2023-12-31 2025-07-03 Kla Corporation Calibration for in-plane distortion tool-to-tool matching
WO2025184185A1 (en) * 2024-02-28 2025-09-04 Tignis, Inc. Determination of thin film pattern to compensate substrate warpage
US12510831B2 (en) 2024-03-11 2025-12-30 Kla Corporation Robust and accurate overlay target design for CMP
US20260068690A1 (en) * 2024-09-04 2026-03-05 Tokyo Electron Limited Fill shape optimization for substrate bonding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015504170A (ja) 2012-01-18 2015-02-05 ユニヴェルシタ・デグリ・ストゥディ・ローマ・トレ 材料のポアソン比および残留応力を測定するための方法
JP2016538717A (ja) 2013-10-29 2016-12-08 ケーエルエー−テンカー コーポレイション プロセス誘起による歪みの予測、ならびにオーバーレイ誤差のフィードフォワード及びフィードバック修正
JP2017122716A (ja) 2015-12-07 2017-07-13 ウルトラテック インク Cgs干渉分光法を用いた処理制御のためにプロセス誘導ウエハ形状を特徴化するシステムおよび方法
JP2018041080A (ja) 2016-09-05 2018-03-15 東京エレクトロン株式会社 半導体プロセッシング中のオーバレイを制御するための湾曲を制御する応力の位置特定チューニング

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL275714A (https=) * 1961-03-09 1900-01-01
EP1089328A1 (en) * 1999-09-29 2001-04-04 Infineon Technologies AG Method for manufacturing of a semiconductor device
US8183104B2 (en) 2010-07-07 2012-05-22 Hobbs Christopher C Method for dual-channel nanowire FET device
EP2463892B1 (de) * 2010-12-13 2013-04-03 EV Group E. Thallner GmbH Einrichtung, Vorrichtung und Verfahren zur Ermittlung von Ausrichtungsfehlern
JP2012151670A (ja) * 2011-01-19 2012-08-09 Renesas Electronics Corp 画像投影システム及び半導体集積回路
FR2972848A1 (fr) * 2011-03-18 2012-09-21 Soitec Silicon On Insulator Appareil et procédé de collage par adhésion moléculaire avec minimisation de déformations locales
US9123567B2 (en) 2011-12-19 2015-09-01 Intel Corporation CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
JP5925579B2 (ja) * 2012-04-25 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び画像処理方法
US9158209B2 (en) * 2012-10-19 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of overlay prediction
US20150192404A1 (en) * 2013-03-31 2015-07-09 Kla-Tencor Corporation Reducing registration error of front and back wafer surfaces utilizing a see-through calibration wafer
US9595525B2 (en) 2014-02-10 2017-03-14 International Business Machines Corporation Semiconductor device including nanowire transistors with hybrid channels
US9269607B2 (en) * 2014-06-17 2016-02-23 Globalfoundries Inc. Wafer stress control with backside patterning
US9779202B2 (en) * 2015-06-22 2017-10-03 Kla-Tencor Corporation Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements
US10377665B2 (en) * 2015-11-19 2019-08-13 Varian Semiconductor Equipment Associates, Inc. Modifying bulk properties of a glass substrate
US9466538B1 (en) * 2015-11-25 2016-10-11 Globalfoundries Inc. Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process
KR102232042B1 (ko) * 2016-10-17 2021-03-25 에이에스엠엘 네델란즈 비.브이. 기판의 파라미터 변동을 보정하기 위한 처리 장치 및 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015504170A (ja) 2012-01-18 2015-02-05 ユニヴェルシタ・デグリ・ストゥディ・ローマ・トレ 材料のポアソン比および残留応力を測定するための方法
JP2016538717A (ja) 2013-10-29 2016-12-08 ケーエルエー−テンカー コーポレイション プロセス誘起による歪みの予測、ならびにオーバーレイ誤差のフィードフォワード及びフィードバック修正
JP2017122716A (ja) 2015-12-07 2017-07-13 ウルトラテック インク Cgs干渉分光法を用いた処理制御のためにプロセス誘導ウエハ形状を特徴化するシステムおよび方法
JP2018041080A (ja) 2016-09-05 2018-03-15 東京エレクトロン株式会社 半導体プロセッシング中のオーバレイを制御するための湾曲を制御する応力の位置特定チューニング

Also Published As

Publication number Publication date
US20180342410A1 (en) 2018-11-29
US10622233B2 (en) 2020-04-14
CN110807273A (zh) 2020-02-18
JP2020021076A (ja) 2020-02-06
TW202025235A (zh) 2020-07-01
KR102558635B1 (ko) 2023-07-21
CN110807273B (zh) 2024-05-14
TWI790391B (zh) 2023-01-21
KR20200015426A (ko) 2020-02-12

Similar Documents

Publication Publication Date Title
JP7118928B2 (ja) 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善
TWI632627B (zh) 程序引入失真之預測以及疊對誤差之前饋及反饋校正
TWI573215B (zh) 模擬由於半導體晶圓固持之平面內失真之基於有限元素模型的預測之系統及方法
JP5634864B2 (ja) リソグラフィック・プロセスに於ける、プロセス制御方法およびプロセス制御装置
JP5758406B2 (ja) 基板トポグラフィならびにそのリソグラフィ・デフォーカスおよびオーバーレイとの関係についてのサイトに基づく定量化
KR102460056B1 (ko) Cgs 간섭측정을 이용한 공정 제어를 위해 공정-유도된 웨이퍼 형상을 특징짓는 시스템 및 방법
CN113406859B (zh) 光学邻近修正模型的建模方法
JP2004118194A (ja) マスク設計における基板トポグラフィ補償:アンカー付きトポグラフィによる3dopc
TWI882335B (zh) 改善基板失真的方法
TWI640050B (zh) 基於用之最佳集成晶片製造效能之設計改良的增強型圖案化晶圓幾何量測
KR20240144167A (ko) 열 구역을 이용한 국소 응력 처리 튜닝을 통한 인-시투 리소그래피 패턴 향상
JP2020060666A (ja) マスクパターン補正システム、及び該補正システムを利用する半導体製造方法
TW201432831A (zh) 校正目標値的方法以及用來校正該目標値的處理系統
JP7445003B2 (ja) マルチステッププロセス検査方法
TWI681479B (zh) 用於分析半導體晶圓之處理的方法及裝置
JPH08203817A (ja) X線マスクの作製方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210909

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210909

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220413

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220419

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220617

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220705

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220803

R150 Certificate of patent or registration of utility model

Ref document number: 7118928

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250