JP2020021076A5 - - Google Patents

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Publication number
JP2020021076A5
JP2020021076A5 JP2019143000A JP2019143000A JP2020021076A5 JP 2020021076 A5 JP2020021076 A5 JP 2020021076A5 JP 2019143000 A JP2019143000 A JP 2019143000A JP 2019143000 A JP2019143000 A JP 2019143000A JP 2020021076 A5 JP2020021076 A5 JP 2020021076A5
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JP
Japan
Prior art keywords
semiconductor wafer
wafer
pattern
distortion
pixel
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JP2019143000A
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English (en)
Japanese (ja)
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JP2020021076A (ja
JP7118928B2 (ja
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Priority claimed from US16/054,725 external-priority patent/US10622233B2/en
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JP2019143000A 2018-08-03 2019-08-02 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善 Active JP7118928B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/054,725 US10622233B2 (en) 2016-09-05 2018-08-03 Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer
US16/054725 2018-08-03

Publications (3)

Publication Number Publication Date
JP2020021076A JP2020021076A (ja) 2020-02-06
JP2020021076A5 true JP2020021076A5 (https=) 2021-10-21
JP7118928B2 JP7118928B2 (ja) 2022-08-16

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JP2019143000A Active JP7118928B2 (ja) 2018-08-03 2019-08-02 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善

Country Status (5)

Country Link
US (1) US10622233B2 (https=)
JP (1) JP7118928B2 (https=)
KR (1) KR102558635B1 (https=)
CN (1) CN110807273B (https=)
TW (1) TWI790391B (https=)

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US11994807B2 (en) 2022-05-03 2024-05-28 Tokyo Electron Limited In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
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JP2025516535A (ja) * 2022-05-13 2025-05-30 アプライド マテリアルズ インコーポレイテッド 基板曲率を使用して面外歪みを補償するためのドーズマッピング
US20240103385A1 (en) * 2022-09-28 2024-03-28 Applied Materials, Inc. Frequency and Amplitude Modulation of Implant Dose for Stress Management
US20250028294A1 (en) * 2023-07-18 2025-01-23 Applied Materials, Inc. Measurement of inherent substrate distortion
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