CN110807273B - 基于半导体晶片的局部畸变的确定的全局晶片畸变的改善 - Google Patents
基于半导体晶片的局部畸变的确定的全局晶片畸变的改善 Download PDFInfo
- Publication number
- CN110807273B CN110807273B CN201910711753.6A CN201910711753A CN110807273B CN 110807273 B CN110807273 B CN 110807273B CN 201910711753 A CN201910711753 A CN 201910711753A CN 110807273 B CN110807273 B CN 110807273B
- Authority
- CN
- China
- Prior art keywords
- wafer
- distortion
- semiconductor wafer
- pattern
- backside
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T5/00—Image enhancement or restoration
- G06T5/80—Geometric correction
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
- H10P74/238—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/70525—Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/706835—Metrology information management or control
- G03F7/706837—Data analysis, e.g. filtering, weighting, flyer removal, fingerprints or root cause analysis
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
- G03F7/70783—Handling stress or warp of chucks, masks or workpieces, e.g. to compensate for imaging errors or considerations related to warpage of masks or workpieces due to their own weight
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0431—Apparatus for thermal treatment
- H10P72/0436—Apparatus for thermal treatment mainly by radiation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0448—Apparatus for applying a liquid, a resin, an ink or the like
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
- H10P72/0616—Monitoring of warpages, curvatures, damages, defects or the like
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
- H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
- H10P72/7614—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
- H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/27—Structural arrangements therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/27—Structural arrangements therefor
- H10P74/273—Interconnections for measuring or testing, e.g. probe pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
- H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
- H10P76/2041—Photolithographic processes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/054,725 US10622233B2 (en) | 2016-09-05 | 2018-08-03 | Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer |
| US16/054,725 | 2018-08-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110807273A CN110807273A (zh) | 2020-02-18 |
| CN110807273B true CN110807273B (zh) | 2024-05-14 |
Family
ID=69487426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910711753.6A Active CN110807273B (zh) | 2018-08-03 | 2019-08-02 | 基于半导体晶片的局部畸变的确定的全局晶片畸变的改善 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10622233B2 (https=) |
| JP (1) | JP7118928B2 (https=) |
| KR (1) | KR102558635B1 (https=) |
| CN (1) | CN110807273B (https=) |
| TW (1) | TWI790391B (https=) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3457213A1 (en) * | 2017-09-18 | 2019-03-20 | ASML Netherlands B.V. | Methods and apparatus for use in a device manufacturing method |
| US10847419B2 (en) * | 2018-03-14 | 2020-11-24 | Raytheon Company | Stress compensation and relief in bonded wafers |
| CN112585540B (zh) * | 2018-08-22 | 2024-09-17 | Asml荷兰有限公司 | 量测设备 |
| US11393118B2 (en) | 2019-06-18 | 2022-07-19 | Kla Corporation | Metrics for asymmetric wafer shape characterization |
| US11879170B2 (en) | 2019-08-14 | 2024-01-23 | Massachusetts Institute Of Technology | Stress patterning systems and methods for manufacturing free-form deformations in thin substrates |
| KR20220167387A (ko) | 2020-05-14 | 2022-12-20 | 에이에스엠엘 네델란즈 비.브이. | 제품 피쳐에 대한 분해능상 계측을 사용하는 웨이퍼 정렬 방법 |
| US12276922B2 (en) | 2020-05-22 | 2025-04-15 | Tokyo Electron Limited | Backside deposition tuning of stress to control wafer bow in semiconductor processing |
| US11637043B2 (en) | 2020-11-03 | 2023-04-25 | Applied Materials, Inc. | Analyzing in-plane distortion |
| US11829077B2 (en) * | 2020-12-11 | 2023-11-28 | Kla Corporation | System and method for determining post bonding overlay |
| JP7611274B2 (ja) * | 2021-02-03 | 2025-01-09 | 東京エレクトロン株式会社 | 膜厚分析方法、膜厚分析装置及び記憶媒体 |
| TWI889613B (zh) * | 2021-04-27 | 2025-07-01 | 美商應用材料股份有限公司 | 用於半導體處理的應力與覆蓋管理 |
| US12469725B2 (en) | 2021-06-27 | 2025-11-11 | Delta Design, Inc. | Method for determining corrective film pattern to reduce semiconductor wafer bow |
| US12394618B2 (en) | 2021-07-08 | 2025-08-19 | Tokyo Electron Limited | Method of adjusting wafer shape using multi-directional actuation films |
| US12051608B2 (en) * | 2021-07-20 | 2024-07-30 | Changxin Memory Technologies, Inc. | Method for adjusting wafer deformation and semiconductor structure |
| US11782411B2 (en) * | 2021-07-28 | 2023-10-10 | Kla Corporation | System and method for mitigating overlay distortion patterns caused by a wafer bonding tool |
| KR20230048952A (ko) * | 2021-10-05 | 2023-04-12 | 삼성전자주식회사 | 풀-칩 레이아웃을 이용한 레이아웃 검증 시스템 및 이를 이용한 레이아웃 검증 방법 |
| US12001147B2 (en) | 2021-11-19 | 2024-06-04 | Tokyo Electron Limited | Precision multi-axis photolithography alignment correction using stressor film |
| US20250028254A1 (en) * | 2021-12-06 | 2025-01-23 | Asml Netherlands B.V. | Methods of determining a mechanical property of a layer applied to a substrate, and associated devices |
| EP4202551A1 (en) * | 2021-12-23 | 2023-06-28 | ASML Netherlands B.V. | Methods of determining a mechanical property of a layer applied to a substrate, and associated devices |
| WO2023108530A1 (en) * | 2021-12-16 | 2023-06-22 | Yangtze Memory Technologies Co., Ltd. | Prediction of wafer flatness |
| US11994807B2 (en) | 2022-05-03 | 2024-05-28 | Tokyo Electron Limited | In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones |
| KR20250008925A (ko) * | 2022-05-13 | 2025-01-16 | 어플라이드 머티어리얼스, 인코포레이티드 | 개선된 분해능을 갖는 기판 곡률 제어용 도즈 매핑 및 기판 회전 |
| JP2025516535A (ja) * | 2022-05-13 | 2025-05-30 | アプライド マテリアルズ インコーポレイテッド | 基板曲率を使用して面外歪みを補償するためのドーズマッピング |
| US20240103385A1 (en) * | 2022-09-28 | 2024-03-28 | Applied Materials, Inc. | Frequency and Amplitude Modulation of Implant Dose for Stress Management |
| US20250028294A1 (en) * | 2023-07-18 | 2025-01-23 | Applied Materials, Inc. | Measurement of inherent substrate distortion |
| US20250216188A1 (en) * | 2023-12-31 | 2025-07-03 | Kla Corporation | Calibration for in-plane distortion tool-to-tool matching |
| WO2025184185A1 (en) * | 2024-02-28 | 2025-09-04 | Tignis, Inc. | Determination of thin film pattern to compensate substrate warpage |
| US12510831B2 (en) | 2024-03-11 | 2025-12-30 | Kla Corporation | Robust and accurate overlay target design for CMP |
| US20260068690A1 (en) * | 2024-09-04 | 2026-03-05 | Tokyo Electron Limited | Fill shape optimization for substrate bonding |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3239611A (en) * | 1961-03-09 | 1966-03-08 | Siemens Ag | Converting mechanical into electrical oscillations |
| US9466538B1 (en) * | 2015-11-25 | 2016-10-11 | Globalfoundries Inc. | Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process |
| CN107799451A (zh) * | 2016-09-05 | 2018-03-13 | 东京毅力科创株式会社 | 半导体加工中控制曲度以控制叠对的位置特定的应力调节 |
| WO2018072961A1 (en) * | 2016-10-17 | 2018-04-26 | Asml Netherlands B.V. | A processing apparatus and a method for correcting a parameter variation across a substrate |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1089328A1 (en) * | 1999-09-29 | 2001-04-04 | Infineon Technologies AG | Method for manufacturing of a semiconductor device |
| US8183104B2 (en) | 2010-07-07 | 2012-05-22 | Hobbs Christopher C | Method for dual-channel nanowire FET device |
| EP2463892B1 (de) * | 2010-12-13 | 2013-04-03 | EV Group E. Thallner GmbH | Einrichtung, Vorrichtung und Verfahren zur Ermittlung von Ausrichtungsfehlern |
| JP2012151670A (ja) * | 2011-01-19 | 2012-08-09 | Renesas Electronics Corp | 画像投影システム及び半導体集積回路 |
| FR2972848A1 (fr) * | 2011-03-18 | 2012-09-21 | Soitec Silicon On Insulator | Appareil et procédé de collage par adhésion moléculaire avec minimisation de déformations locales |
| US9123567B2 (en) | 2011-12-19 | 2015-09-01 | Intel Corporation | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture |
| US9012284B2 (en) | 2011-12-23 | 2015-04-21 | Intel Corporation | Nanowire transistor devices and forming techniques |
| ITRM20120017A1 (it) * | 2012-01-18 | 2013-07-19 | Univ Degli Studi Roma Tre | Metodo per la misura del rapporto di poisson e dello stress residuo |
| JP5925579B2 (ja) * | 2012-04-25 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | 半導体装置、電子装置、及び画像処理方法 |
| US9158209B2 (en) * | 2012-10-19 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of overlay prediction |
| US20150192404A1 (en) * | 2013-03-31 | 2015-07-09 | Kla-Tencor Corporation | Reducing registration error of front and back wafer surfaces utilizing a see-through calibration wafer |
| US10401279B2 (en) * | 2013-10-29 | 2019-09-03 | Kla-Tencor Corporation | Process-induced distortion prediction and feedforward and feedback correction of overlay errors |
| US9595525B2 (en) | 2014-02-10 | 2017-03-14 | International Business Machines Corporation | Semiconductor device including nanowire transistors with hybrid channels |
| US9269607B2 (en) * | 2014-06-17 | 2016-02-23 | Globalfoundries Inc. | Wafer stress control with backside patterning |
| US9779202B2 (en) * | 2015-06-22 | 2017-10-03 | Kla-Tencor Corporation | Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements |
| US10377665B2 (en) * | 2015-11-19 | 2019-08-13 | Varian Semiconductor Equipment Associates, Inc. | Modifying bulk properties of a glass substrate |
| NL2017860B1 (en) * | 2015-12-07 | 2017-07-27 | Ultratech Inc | Systems and methods of characterizing process-induced wafer shape for process control using cgs interferometry |
-
2018
- 2018-08-03 US US16/054,725 patent/US10622233B2/en active Active
-
2019
- 2019-07-30 TW TW108126894A patent/TWI790391B/zh active
- 2019-08-02 JP JP2019143000A patent/JP7118928B2/ja active Active
- 2019-08-02 KR KR1020190094412A patent/KR102558635B1/ko active Active
- 2019-08-02 CN CN201910711753.6A patent/CN110807273B/zh active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3239611A (en) * | 1961-03-09 | 1966-03-08 | Siemens Ag | Converting mechanical into electrical oscillations |
| US9466538B1 (en) * | 2015-11-25 | 2016-10-11 | Globalfoundries Inc. | Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process |
| CN107799451A (zh) * | 2016-09-05 | 2018-03-13 | 东京毅力科创株式会社 | 半导体加工中控制曲度以控制叠对的位置特定的应力调节 |
| WO2018072961A1 (en) * | 2016-10-17 | 2018-04-26 | Asml Netherlands B.V. | A processing apparatus and a method for correcting a parameter variation across a substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| US20180342410A1 (en) | 2018-11-29 |
| US10622233B2 (en) | 2020-04-14 |
| CN110807273A (zh) | 2020-02-18 |
| JP2020021076A (ja) | 2020-02-06 |
| TW202025235A (zh) | 2020-07-01 |
| KR102558635B1 (ko) | 2023-07-21 |
| TWI790391B (zh) | 2023-01-21 |
| KR20200015426A (ko) | 2020-02-12 |
| JP7118928B2 (ja) | 2022-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110807273B (zh) | 基于半导体晶片的局部畸变的确定的全局晶片畸变的改善 | |
| TWI632627B (zh) | 程序引入失真之預測以及疊對誤差之前饋及反饋校正 | |
| JP5059909B2 (ja) | マイクロリソグラフィにおけるアラインメントとオーバーレイを改善するシステムおよび方法 | |
| TWI573215B (zh) | 模擬由於半導體晶圓固持之平面內失真之基於有限元素模型的預測之系統及方法 | |
| JP5634864B2 (ja) | リソグラフィック・プロセスに於ける、プロセス制御方法およびプロセス制御装置 | |
| CN108828896B (zh) | 添加亚分辨率辅助图形的方法及该方法的应用 | |
| CN113406859B (zh) | 光学邻近修正模型的建模方法 | |
| CN110546574A (zh) | 维护工艺指印集合 | |
| TW201706725A (zh) | 微影裝置之校準方法、使用該方法之微影裝置及元件製造方法 | |
| CN109656093B (zh) | 设计光掩模的布局的方法以及制造光掩模的方法 | |
| CN109828433A (zh) | 校正掩模布局的方法和使用其制造半导体器件的方法 | |
| CN110320741A (zh) | 用于形成自适应层的装置及其使用方法 | |
| JP2025507300A (ja) | ヒートゾーンを使用する局所的応力処理調整によるインサイチュリソグラフィパターン強化 | |
| JP2020060666A (ja) | マスクパターン補正システム、及び該補正システムを利用する半導体製造方法 | |
| TW201432831A (zh) | 校正目標値的方法以及用來校正該目標値的處理系統 | |
| CN118339635A (zh) | 使用应力源膜的精度多轴光刻对准校正 | |
| US8196071B2 (en) | Creating mask data of integrated circuit patterns using calculated etching conversion difference | |
| CN120559952A (zh) | 一种光刻机套刻误差补偿方法、装置、系统和介质 | |
| TW202509686A (zh) | 用於將一基板區域量測資料模型化之方法及其相關裝置 | |
| JP4657646B2 (ja) | マスクパターン配置方法、マスク作製方法、半導体装置の製造方法、プログラム |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |