JP7100219B1 - 半導体装置および半導体モジュール - Google Patents

半導体装置および半導体モジュール Download PDF

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Publication number
JP7100219B1
JP7100219B1 JP2022529718A JP2022529718A JP7100219B1 JP 7100219 B1 JP7100219 B1 JP 7100219B1 JP 2022529718 A JP2022529718 A JP 2022529718A JP 2022529718 A JP2022529718 A JP 2022529718A JP 7100219 B1 JP7100219 B1 JP 7100219B1
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Japan
Prior art keywords
semiconductor device
semiconductor
semiconductor layer
metal wiring
gate pad
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JP2022529718A
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English (en)
Japanese (ja)
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JPWO2022209346A1 (https=
JPWO2022209346A5 (https=
Inventor
興輝 山本
伸一 秋吉
亮一 網師本
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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Application filed by Nuvoton Technology Corp Japan filed Critical Nuvoton Technology Corp Japan
Priority claimed from PCT/JP2022/005414 external-priority patent/WO2022209346A1/ja
Priority to JP2022105208A priority Critical patent/JP7177961B2/ja
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Publication of JPWO2022209346A1 publication Critical patent/JPWO2022209346A1/ja
Publication of JPWO2022209346A5 publication Critical patent/JPWO2022209346A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2022529718A 2021-03-29 2022-02-10 半導体装置および半導体モジュール Active JP7100219B1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022105208A JP7177961B2 (ja) 2021-03-29 2022-06-30 半導体装置および半導体モジュール

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163167348P 2021-03-29 2021-03-29
US63/167,348 2021-03-29
PCT/JP2022/005414 WO2022209346A1 (ja) 2021-03-29 2022-02-10 半導体装置および半導体モジュール

Related Child Applications (1)

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JP2022105208A Division JP7177961B2 (ja) 2021-03-29 2022-06-30 半導体装置および半導体モジュール

Publications (3)

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JP7100219B1 true JP7100219B1 (ja) 2022-07-12
JPWO2022209346A1 JPWO2022209346A1 (https=) 2022-10-06
JPWO2022209346A5 JPWO2022209346A5 (https=) 2023-02-28

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JP2022105208A Active JP7177961B2 (ja) 2021-03-29 2022-06-30 半導体装置および半導体モジュール

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US (2) US12165999B2 (https=)
JP (2) JP7100219B1 (https=)
KR (1) KR102629278B1 (https=)
CN (1) CN116250088B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026079378A1 (ja) * 2024-10-09 2026-04-16 ヌヴォトンテクノロジージャパン株式会社 半導体装置および積層構造体

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7728714B2 (ja) * 2022-02-03 2025-08-25 ルネサスエレクトロニクス株式会社 半導体装置および回路装置
WO2025197135A1 (ja) * 2024-03-21 2025-09-25 ヌヴォトンテクノロジージャパン株式会社 半導体装置
JP7651085B1 (ja) * 2024-03-21 2025-03-25 ヌヴォトンテクノロジージャパン株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368217A (ja) * 2001-06-08 2002-12-20 Sanyo Electric Co Ltd １チップデュアル型絶縁ゲート型半導体装置
JP2004502293A (ja) * 2000-02-10 2004-01-22 インターナショナル・レクチファイヤー・コーポレーション 単一表面上のバンプコンタクトを有する垂直伝導フリップチップ半導体デバイス
JP2019169492A (ja) * 2018-03-21 2019-10-03 株式会社東芝 半導体装置
WO2020129786A1 (ja) * 2018-12-19 2020-06-25 パナソニックセミコンダクターソリューションズ株式会社 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4453587B2 (ja) * 2005-03-24 2010-04-21 株式会社デンソー 加速度センサ
US7898831B2 (en) * 2008-05-09 2011-03-01 Alpha and Omega Semiconductor Inc. Device and method for limiting drain-source voltage of transformer-coupled push pull power conversion circuit
JP5980515B2 (ja) * 2012-02-06 2016-08-31 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 絶縁ゲート型半導体装置
JP5990401B2 (ja) 2012-05-29 2016-09-14 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6063713B2 (ja) * 2012-11-08 2017-01-18 ルネサスエレクトロニクス株式会社 電池保護システム
JP6348703B2 (ja) 2013-11-12 2018-06-27 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
CN111640742B (zh) 2015-07-01 2021-04-20 新唐科技日本株式会社 半导体装置
JP6795888B2 (ja) 2016-01-06 2020-12-02 力智電子股▲フン▼有限公司ｕＰＩ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｃｏｒｐ． 半導体装置及びそれを用いた携帯機器
JP6447946B1 (ja) 2018-01-19 2019-01-09 パナソニックＩｐマネジメント株式会社 半導体装置および半導体モジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004502293A (ja) * 2000-02-10 2004-01-22 インターナショナル・レクチファイヤー・コーポレーション 単一表面上のバンプコンタクトを有する垂直伝導フリップチップ半導体デバイス
JP2002368217A (ja) * 2001-06-08 2002-12-20 Sanyo Electric Co Ltd １チップデュアル型絶縁ゲート型半導体装置
JP2019169492A (ja) * 2018-03-21 2019-10-03 株式会社東芝 半導体装置
WO2020129786A1 (ja) * 2018-12-19 2020-06-25 パナソニックセミコンダクターソリューションズ株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026079378A1 (ja) * 2024-10-09 2026-04-16 ヌヴォトンテクノロジージャパン株式会社 半導体装置および積層構造体

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Publication number Publication date
KR20230043220A (ko) 2023-03-30
JP7177961B2 (ja) 2022-11-24
CN116250088B (zh) 2025-12-26
KR102629278B1 (ko) 2024-01-25
JPWO2022209346A1 (https=) 2022-10-06
US12080664B2 (en) 2024-09-03
CN116250088A (zh) 2023-06-09
US20230307393A1 (en) 2023-09-28
US20240030167A1 (en) 2024-01-25
JP2022153382A (ja) 2022-10-12
US12165999B2 (en) 2024-12-10

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