JP7097792B2 - メモリ装置及びその動作方法 - Google Patents

メモリ装置及びその動作方法 Download PDF

Info

Publication number
JP7097792B2
JP7097792B2 JP2018186436A JP2018186436A JP7097792B2 JP 7097792 B2 JP7097792 B2 JP 7097792B2 JP 2018186436 A JP2018186436 A JP 2018186436A JP 2018186436 A JP2018186436 A JP 2018186436A JP 7097792 B2 JP7097792 B2 JP 7097792B2
Authority
JP
Japan
Prior art keywords
memory
memory cell
read
state
read voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018186436A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019102117A (ja
JP2019102117A5 (enExample
Inventor
菜▲うく▼ 林
太熙 羅
禎 鮮于
▲よん▼▲じゅん▼ 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2019102117A publication Critical patent/JP2019102117A/ja
Publication of JP2019102117A5 publication Critical patent/JP2019102117A5/ja
Application granted granted Critical
Publication of JP7097792B2 publication Critical patent/JP7097792B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/003Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0033Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0097Erasing, e.g. resetting, circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • G11C2013/0047Read destroying or disturbing the data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • G11C2013/0057Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10Resistive cells; Technology aspects
    • G11C2213/15Current-voltage curve
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/72Array wherein the access device being a diode

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
JP2018186436A 2017-12-05 2018-10-01 メモリ装置及びその動作方法 Active JP7097792B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170165843A KR102401183B1 (ko) 2017-12-05 2017-12-05 메모리 장치 및 그 동작 방법
KR10-2017-0165843 2017-12-05

Publications (3)

Publication Number Publication Date
JP2019102117A JP2019102117A (ja) 2019-06-24
JP2019102117A5 JP2019102117A5 (enExample) 2021-09-24
JP7097792B2 true JP7097792B2 (ja) 2022-07-08

Family

ID=66548389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018186436A Active JP7097792B2 (ja) 2017-12-05 2018-10-01 メモリ装置及びその動作方法

Country Status (5)

Country Link
US (1) US10580488B2 (enExample)
JP (1) JP7097792B2 (enExample)
KR (1) KR102401183B1 (enExample)
CN (1) CN109872751B (enExample)
DE (1) DE102018128329A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102427895B1 (ko) * 2018-02-08 2022-08-02 에스케이하이닉스 주식회사 저항 메모리 소자의 읽기 방법
KR102701814B1 (ko) * 2019-02-27 2024-09-03 에스케이하이닉스 주식회사 효율적인 리드 동작을 수행하는 비휘발성 메모리 장치 및 이를 이용하는 시스템
US10867671B1 (en) * 2019-07-02 2020-12-15 Micron Technology, Inc. Techniques for applying multiple voltage pulses to select a memory cell
US10942655B2 (en) * 2019-07-09 2021-03-09 Seagate Technology Llc Mitigating data errors in a storage device
JP2023025932A (ja) * 2021-08-11 2023-02-24 ソニーセミコンダクタソリューションズ株式会社 メモリモジュール
FR3155310A1 (fr) * 2023-11-10 2025-05-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Estimation de l’état initial d’un élément résistif

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016084497A1 (ja) 2014-11-26 2016-06-02 ソニー株式会社 メモリシステム、記憶装置、および、メモリシステムの制御方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768665B2 (en) 2002-08-05 2004-07-27 Intel Corporation Refreshing memory cells of a phase change material memory device
JP4189395B2 (ja) * 2004-07-28 2008-12-03 シャープ株式会社 不揮発性半導体記憶装置及び読み出し方法
KR100610014B1 (ko) * 2004-09-06 2006-08-09 삼성전자주식회사 리키지 전류 보상 가능한 반도체 메모리 장치
US7193898B2 (en) * 2005-06-20 2007-03-20 Sandisk Corporation Compensation currents in non-volatile memory read operations
US7679980B2 (en) 2006-11-21 2010-03-16 Qimonda North America Corp. Resistive memory including selective refresh operation
US7990761B2 (en) 2008-03-31 2011-08-02 Ovonyx, Inc. Immunity of phase change material to disturb in the amorphous phase
KR20090126587A (ko) * 2008-06-04 2009-12-09 삼성전자주식회사 상 변화 메모리 장치 및 그것의 읽기 방법
US8406033B2 (en) 2009-06-22 2013-03-26 Macronix International Co., Ltd. Memory device and method for sensing and fixing margin cells
KR20110107190A (ko) 2010-03-24 2011-09-30 삼성전자주식회사 저항성 메모리의 마모 셀 관리 방법 및 장치
US8467237B2 (en) * 2010-10-15 2013-06-18 Micron Technology, Inc. Read distribution management for phase change memory
US20130336047A1 (en) 2012-04-24 2013-12-19 Being Advanced Memory Corporation Cell Refresh in Phase Change Memory
US8885388B2 (en) 2012-10-24 2014-11-11 Marvell World Trade Ltd. Apparatus and method for reforming resistive memory cells
KR102023358B1 (ko) * 2012-10-29 2019-09-20 삼성전자 주식회사 저항체를 이용한 비휘발성 메모리 장치 및 그 구동 방법
KR20140090879A (ko) * 2013-01-10 2014-07-18 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 읽기 방법
US9165683B2 (en) 2013-09-23 2015-10-20 Sandisk Technologies Inc. Multi-word line erratic programming detection
US9257175B2 (en) 2013-09-26 2016-02-09 Intel Corporation Refresh of data stored in a cross-point non-volatile memory
US9286975B2 (en) 2014-03-11 2016-03-15 Intel Corporation Mitigating read disturb in a cross-point memory
US9275730B2 (en) 2014-04-11 2016-03-01 Micron Technology, Inc. Apparatuses and methods of reading memory cells based on response to a test pulse
KR20160074238A (ko) * 2014-12-18 2016-06-28 에스케이하이닉스 주식회사 전자 장치 및 전자 장치의 동작 방법
US9437293B1 (en) 2015-03-27 2016-09-06 Intel Corporation Integrated setback read with reduced snapback disturb
US9613691B2 (en) 2015-03-27 2017-04-04 Intel Corporation Apparatus and method for drift cancellation in a memory
CN104821179B (zh) * 2015-04-16 2017-09-26 江苏时代全芯存储科技有限公司 记忆体驱动电路
US10482960B2 (en) 2016-02-17 2019-11-19 Intel Corporation Dual demarcation voltage sensing before writes
US9721657B1 (en) * 2016-04-02 2017-08-01 Intel Corporation Managing threshold voltage shift in nonvolatile memory
KR102657562B1 (ko) * 2016-12-02 2024-04-17 에스케이하이닉스 주식회사 비휘발성 메모리 장치

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016084497A1 (ja) 2014-11-26 2016-06-02 ソニー株式会社 メモリシステム、記憶装置、および、メモリシステムの制御方法

Also Published As

Publication number Publication date
KR20190066271A (ko) 2019-06-13
JP2019102117A (ja) 2019-06-24
US10580488B2 (en) 2020-03-03
KR102401183B1 (ko) 2022-05-24
DE102018128329A1 (de) 2019-06-06
CN109872751B (zh) 2024-09-10
US20190172531A1 (en) 2019-06-06
CN109872751A (zh) 2019-06-11

Similar Documents

Publication Publication Date Title
JP7097791B2 (ja) メモリ装置及びその動作方法
JP7097792B2 (ja) メモリ装置及びその動作方法
US7830705B2 (en) Multi-level phase change memory device and related methods
KR101374319B1 (ko) 가변 저항 메모리 장치 및 그것의 동작 방법
US8345464B2 (en) Resistive memory devices having a stacked structure and methods of operation thereof
US8050083B2 (en) Phase change memory device and write method thereof
KR102215359B1 (ko) 비휘발성 메모리 장치와 그 센싱 방법
KR20110027939A (ko) 상변화 메모리 장치, 이를 구비하는 메모리 시스템 및 이의 프로그램 방법
KR102187116B1 (ko) 비휘발성 메모리 장치와 이를 포함하는 메모리 시스템, 및 비휘발성 메모리 장치의 구동 방법
US11238927B2 (en) Memory device having program current adjustible based on detected holding voltage
CN110910931B (zh) 存储器设备
KR20140090879A (ko) 불휘발성 메모리 장치 및 그것의 읽기 방법
KR20100123136A (ko) 비휘발성 메모리 장치
JP7130523B2 (ja) メモリー装置
TWI853052B (zh) 電阻式記憶體裝置及其操作方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210810

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210810

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220614

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220628

R150 Certificate of patent or registration of utility model

Ref document number: 7097792

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250