JP7096741B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7096741B2 JP7096741B2 JP2018169857A JP2018169857A JP7096741B2 JP 7096741 B2 JP7096741 B2 JP 7096741B2 JP 2018169857 A JP2018169857 A JP 2018169857A JP 2018169857 A JP2018169857 A JP 2018169857A JP 7096741 B2 JP7096741 B2 JP 7096741B2
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- 239000004065 semiconductor Substances 0.000 title claims description 122
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 229920005989 resin Polymers 0.000 claims description 57
- 239000011347 resin Substances 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 33
- 229910000679 solder Inorganic materials 0.000 description 17
- 239000011162 core material Substances 0.000 description 14
- 239000012212 insulator Substances 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 238000007689 inspection Methods 0.000 description 8
- 239000008186 active pharmaceutical agent Substances 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000007666 vacuum forming Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/495—Lead-frames or other flat leads
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- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1(a)および(b)は、第1実施形態に係る半導体装置1を示す模式図である。図1(a)は、図1(b)中に示すA-A線に沿った断面を表す模式断面図である。図1(b)は、半導体装置1の下面を表す模式図である。
図7(a)に示すように、支持部材130を剥離し、樹脂部材40の第2面40bを露出させる。
図11(a)~(c)は、第2実施形態に係る半導体装置6~8を示す模式断面図である。図11(a)~(c)は、図1(a)に該当する断面を表す模式図である。半導体装置6~8は、例えば、ベース部材30が実装基板に向き合うようにボンディングされ、半導体チップ10の裏面10bが上方に向くように配置される。
Claims (3)
- 第1基材上に、複数の開口を有する枠部と、前記枠部から前記複数の開口のそれぞれの内側に突出した複数の端子と、を有するフレームを配置し、
前記複数の開口内に位置するように、前記第1基材上に複数の半導体チップを配置し、
前記フレームおよび前記複数の半導体チップを覆う樹脂部材を形成し、
前記樹脂部材の前記第1基材に接する第1表面とは反対側の第2表面上に第2基材を貼り付けた後、前記第1基材を剥離し、前記第1表面に前記フレームおよび前記複数の半導体チップを露出させ、
前記複数の半導体チップと前記複数の端子部とをそれぞれつなぐ複数の配線を形成し、
前記複数の端子部を前記樹脂部材中に残して前記枠部を除去し、前記樹脂部材を複数のパッケージに分割する半導体装置の製造方法。 - 前記第1基材の表面に沿った方向における前記枠部の幅よりも厚いブレードを用いて、前記樹脂部材内に前記複数の端子が残るように前記フレームをハーフカットした後、前記樹脂部材の表面に露出された前記フレームの表面上に金属層を選択的に形成する請求項1記載の半導体装置の製造方法。
- 前記枠部の幅よりも厚いブレードを用いて、前記樹脂部材内に前記複数の端子が残るように前記フレームをカットし、
前記樹脂部材中に残された前記複数の端子の露出面上に金属層を選択的に形成し、
前記第2表面側から前記樹脂部材を薄膜化することにより、前記樹脂部材を前記複数の
パッケージに分割する請求項1記載の半導体装置の製造方法。
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JP2018169857A JP7096741B2 (ja) | 2018-09-11 | 2018-09-11 | 半導体装置の製造方法 |
CN201811442394.0A CN110890340B (zh) | 2018-09-11 | 2018-11-29 | 半导体装置及其制造方法 |
US16/265,091 US11264313B2 (en) | 2018-09-11 | 2019-02-01 | Semiconductor device and method for manufacturing same |
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JP2005038927A (ja) | 2003-07-16 | 2005-02-10 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US20150084171A1 (en) | 2013-09-23 | 2015-03-26 | Stmicroelectronics Pte. Ltd. | No-lead semiconductor package and method of manufacturing the same |
US20170278762A1 (en) | 2016-03-24 | 2017-09-28 | Infineon Technologies Ag | Redirecting solder material to visually inspectable package surface |
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JP3061014B2 (ja) * | 1997-10-08 | 2000-07-10 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP5207896B2 (ja) | 2008-09-18 | 2013-06-12 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US8357564B2 (en) * | 2010-05-17 | 2013-01-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die |
US9257393B1 (en) | 2014-09-29 | 2016-02-09 | Freescale Semiconductor Inc. | Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof |
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JP2005038927A (ja) | 2003-07-16 | 2005-02-10 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US20150084171A1 (en) | 2013-09-23 | 2015-03-26 | Stmicroelectronics Pte. Ltd. | No-lead semiconductor package and method of manufacturing the same |
US20170278762A1 (en) | 2016-03-24 | 2017-09-28 | Infineon Technologies Ag | Redirecting solder material to visually inspectable package surface |
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CN110890340A (zh) | 2020-03-17 |
US11264313B2 (en) | 2022-03-01 |
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CN110890340B (zh) | 2023-10-27 |
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